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| 101 innovation drive san jose, ca 95134 www.altera.com siv5v4-5.8 volume 4: device datasheet and addendum stratix iv device handbook
? 2014 altera corporation. all rights reserved. altera, arria, cy clone, hardcopy, max, megacore , nios, quartus and stratix word s and logos are trademarks of alte ra corporation and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specificat ions in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no respon sibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum iso 9001:2008 registered march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v section i. device datasheet and adde ndum for stratix iv devices chapter 1. dc and switching characte ristics for stratix iv devices electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?7 internal weak pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?11 i/o standard specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?12 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?15 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?15 transceiver performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?16 transceiver datapath pcs latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?47 core performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?47 clock tree specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?47 pll specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?48 dsp block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?50 trimatrix memory block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?51 configuration and jtag specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?52 temperature sensing diode specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?53 chip-wide reset (dev_clrn) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?54 periphery performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?54 high-speed i/o specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?54 oct calibration block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?61 duty cycle distortion (dcd) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?62 i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?62 programmable ioe delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?63 programmable output buffer delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?63 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?64 chapter 2. addendum to the stratix iv device handbook additional information how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 iv contents stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum chapter revision dates the chapters in this document, stratix iv device handbook, were revised on the following dates. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1. dc and switching characte ristics for stratix iv devices revised: march 2014 part number: siv54001-5.8 chapter 2. addendum to the stratix iv device handbook revised: february 2011 part number: siv54002-1.5 vi chapter revision dates stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum section i. device datasheet and addendum for stratix iv devices this section includes the following chapters: revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook. i?2 section i: device datasheet and addendum for stratix iv devices stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum siv54001-5.8 ? 2014 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 4: device datasheet and addendum march 2014 feedback subscribe iso 9001:2008 registered 1. dc and switching characteristics for stratix iv devices this chapter contains the following sections: ?electrical characteristics? ?switching characteristics? ?i/o timing? ?glossary? electrical characteristics this chapter covers the electrical an d switching characteristics for stratix ? iv devices. electrical characteristics include operating conditions and power consumption. switching characteristics include transceiver specifications, core, and periphery performance. this chapter also describe s i/o timing, including programmable i/o element (ioe) delay and progra mmable output buffer delay. f for information regarding the densities and packages of devices in the stratix iv family, refer to the stratix iv device family overview chapter. operating conditions when you use stratix iv devices, they are rated according to a set of defined parameters. to maintain the highest possible performance and reliability of the stratix iv devices, you must consider the operating requirements described in this chapter. stratix iv devices are offered in commercial, industrial, and military grades. commercial devices are offered in ?2 (fastest), ?2, ?3, and ?4 speed grades. industrial devices are offered in ?1, ?2, ?3, and ?4 spee d grades. military devices are offered in ?3 speed grade. for the stratix iv gt ?1 and ?2 speed grade specifications, refer to the ?2/?2 speed grade column. for the stratix iv gt ?3 speed grade specification, refer to the ?3 speed grade column, unless otherwise specified. absolute maximum ratings absolute maximum ratings define the maxi mum operating conditions for stratix iv devices. the values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. the functional operation of the device is not implied for these conditions. march 2014 siv54001-5.8 1?2 chapter 1: dc and switching characteristics for stratix iv devices electrical characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum c conditions other than those listed in table 1?1 , table 1?2 , and table 1?3 may cause permanent damage to the device. addition ally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. table 1?1. absolute maximum ratings for stratix iv devices symbol description minimum maximum unit v cc core voltage and periphery circuitry power supply -0.5 1.35 v v ccpt power supply for programmable power technology -0.5 1.8 v v ccpgm configuration pins power supply -0.5 3.75 v v ccaux auxiliary supply for the programmable power technology -0.5 3.75 v v ccbat battery back-up power supply for design security volatile key register -0.5 3.75 v v ccpd i/o pre-driver power supply -0.5 3.75 v v ccio i/o power supply -0.5 3.9 v v cc_clkin differential clock input power supply -0.5 3.75 v v ccd_pll pll digital power supply -0.5 1.35 v v cca_pll pll analog power supply -0.5 3.75 v v i dc input voltage -0.5 4.0 v i out dc output current per pin -25 40 ma t j operating junction temperature -55 125 c t stg storage temperature (no bias) -65 150 c table 1?2. transceiver power supply absolute maximum ratings for stratix iv gx devices symbol description minimum maximum unit v cca_l transceiver high voltage power (left side) -0.5 3.75 v v cca_r transceiver high voltage power (right side) -0.5 3.75 v v cchip_l transceiver hip digital power (left side) -0.5 1.35 v v cchip_r transceiver hip digital power (right side) -0.5 1.35 v v ccr_l receiver power (left side) -0.5 1.35 v v ccr_r receiver power (right side) -0.5 1.35 v v cct_l transmitter power (left side) -0.5 1.35 v v cct_r transmitter power (right side) -0.5 1.35 v v ccl_gxbln (1) transceiver clock power (left side) -0.5 1.35 v v ccl_gxbrn (1) transceiver clock power (right side) -0.5 1.35 v v cch_gxbln (1) transmitter output buffer power (left side) -0.5 1.8 v v cch_gxbrn (1) transmitter output buffer power (right side) -0.5 1.8 v note to table 1?2 : (1) n = 0, 1, 2, or 3. chapter 1: dc and switching characteristics for stratix iv devices 1?3 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum table 1?3. transceiver power supply absolute maximum ratings for stratix iv gt devices (1) symbol description minimum maximum unit v cca_l transceiver high voltage power (left side) -0.5 3.75 v v cca_r transceiver high voltage power (right side) -0.5 3.75 v v cchip_l transceiver hip digital power (left side) -0.5 1.35 v v cchip_r transceiver hip digital power (right side) -0.5 1.35 v v ccr_l receiver power (left side) -0.5 1.35 v v ccr_r receiver power (right side) -0.5 1.35 v v cct_l transmitter power (left side) -0.5 1.35 v v cct_r transmitter power (right side) -0.5 1.35 v v ccl_gxbln (2) transceiver clock power (left side) -0.5 1.35 v v ccl_gxbrn (2) transceiver clock power (right side) -0.5 1.35 v v cch_gxbln (2) transmitter output buffer power (left side) -0.5 1.8 v v cch_gxbrn (2) transmitter output buffer power (right side) -0.5 1.8 v notes to table 1?3 : (1) for the absolute maximum rati ngs for stratix iv gt engineer ing sample (es1) devices, contact your local altera sales represe ntative. (2) n = 0, 1, 2, or 3. chapter 1: dc and switching characteristics for stratix iv devices 1?4 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum maximum allowed overshoot and undershoot voltage during transitions, input signals may overshoot to the voltage shown in table 1?4 and undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. table 1?4 lists the maximum allowed input oversh oot voltage and the duration of the overshoot voltage as a percentage of device lifetime. the maximum allowed overshoot duration is specified as a percenta ge of high time over the lifetime of the device. a dc signal is equivalent to 100% duty cycle. for example, a signal that overshoots to 4.3 v can only be at 4.3 v for ~5% over the lifetime of the device; for a device lifetime of 10 years, th is amounts to half of a year. temperature overshoot above maximum allowed temperature the maximum allowed operating temperature for stratix iv industrial grade devices is 100 c. it is recommended that the operating temperature of the device is maintained below 100 c at all times. the temperature excursions over 100 c due to internal heating of the device should not ex ceed the number of cycles as specified in the table 1?5 . exceeding the recommended number of cycles may cause solder interconnect failures. altera ? recommends using the strati xiv military grade devices if the application requires operating temperatures over 100 c. table 1?4. maximum allowed overshoot during transitions symbol description condition (v) overshoot duration as % of high time unit vi (ac) ac input voltage 4.0 100.000 % 4.05 79.330 % 4.1 46.270 % 4.15 27.030 % 4.2 15.800 % 4.25 9.240 % 4.3 5.410 % 4.35 3.160 % 4.4 1.850 % 4.45 1.080 % 4.5 0.630 % 4.55 0.370 % 4.6 0.220 % table 1?5. temperature overshoot above maximum allowed temperature description operating temperature ( c) number of cycles over 100 c device operating temperature (c) 100 3200 105 768 110 640 115 480 120 320 125 160 chapter 1: dc and switching characteristics for stratix iv devices 1?5 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum recommended operating conditions this section lists the functional operation limits for ac and dc parameters for stratix iv devices. table 1?6 lists the steady-state voltag e and current values expected from stratix iv devices. power supply ramps must all be strictly monotonic, without plateaus. f for power supply ripple requirements, refer to the device-specific power delivery network (pdn) tool user guide . table 1?6. recommended operating conditions for stratix iv devices (part 1 of 2) symbol description condition minimum typical maximum unit v cc (stratix iv gx and stratix iv e) core voltage and periphery circuitry power supply ? 0.87 0.90 0.93 v v cc (stratix iv gt) core voltage and periphery circuitry power supply ? 0.92 0.95 0.98 v v ccpt power supply for programmable power technology ? 1.45 1.5 1.55 v v ccaux auxiliary supply for the programmable power technology ? 2.375 2.5 2.625 v v ccpd (2) i/o pre-driver (3.0 v) power supply ? 2.85 3.0 3.15 v i/o pre-driver (2.5 v) power supply ? 2.375 2.5 2.625 v v ccio i/o buffers (3.0 v) power supply ? 2.85 3.0 3.15 v i/o buffers (2.5 v) power supply ? 2.375 2.5 2.625 v i/o buffers (1.8 v) power supply ? 1.71 1.8 1.89 v i/o buffers (1.5 v) power supply ? 1.425 1.5 1.575 v i/o buffers (1.2 v) power supply ? 1.14 1.2 1.26 v v ccpgm configuration pins (3.0 v) power supply ? 2.85 3.0 3.15 v configuration pins (2.5 v) power supply ? 2.375 2.5 2.625 v configuration pins (1.8 v) power supply ? 1.71 1.8 1.89 v v cca_pll pll analog voltage regulator power supply ? 2.375 2.5 2.625 v v ccd_pll (stratix iv gx and stratix iv e) pll digital voltage regulator power supply ? 0.87 0.90 0.93 v v ccd_pll (stratix iv gt) pll digital voltage regulator power supply ? 0.92 0.95 0.98 v v cc_clkin differential clock input power supply ? 2.375 2.5 2.625 v v ccbat (1) battery back-up power supply (for design security volatile key register) ?1.2?3.3v v i dc input voltage ? ?0.5 ? 3.6 v v o output voltage ? 0 ? v ccio v t j (stratix iv gx and stratix iv e) operating junction temperature commercial 0 ? 85 c industrial ?40 ? 100 c military ?55 ? 125 c t j (stratix iv gt) operating junction temperature industrial 0 ? 100 c chapter 1: dc and switching characteristics for stratix iv devices 1?6 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum table 1?7 lists the transceiver power supply recommended operating conditions for stratix iv gx devices. table 1?8 lists the recommended operating conditions for the stratix iv gt transceiver power supply. t ramp power supply ramp time normal por (porsel=0) 0.05 ? 100 ms fast por (porsel=1) 0.05 ? 4 ms notes to table 1?6 : (1) if you do not use the volatile se curity key, you may connect the v ccbat to either gnd or a 3.0-v power supply. (2) v ccpd must be 2.5 v when v ccio is 2.5, 1.8, 1.5, or 1.2 v. v ccpd must be 3.0 v when v ccio is 3.0 v. table 1?6. recommended operating conditions for stratix iv devices (part 2 of 2) symbol description condition minimum typical maximum unit table 1?7. transceiver power supply operating conditions for stratix iv gx devices (1) symbol description minimum typical maximum unit v cca_l transceiver high voltage power (left side) 2.85/2.375 3.0/2.5 (2) 3.15/2.625 v v cca_r transceiver high voltage power (right side) v cchip_l transceiver hip digital power (left side) 0.87 0.9 0.93 v v cchip_r transceiver hip digital power (right side) 0.87 0.9 0.93 v v ccr_l receiver power (left side) 1.045 1.1 1.155 v v ccr_r receiver power (right side) 1.045 1.1 1.155 v v cct_l transmitter power (left side) 1.045 1.1 1.155 v v cct_r transmitter power (right side) 1.045 1.1 1.155 v v ccl_gxbln (3) transceiver clock power (left side) 1.05 1.1 1.15 v v ccl_gxbrn (3) transceiver clock power (right side) 1.05 1.1 1.15 v v cch_gxbln (3) transmitter output buffer power (left side) 1.33/1.425 1.4/1.5 (4) 1.47/1.575 v v cch_gxbrn (3) transmitter output buffer power (right side) notes to table 1?7 : (1) transceiver power supplies do not have pow er-on-reset (por) circuitry. after initia l power-up, violati ng the transceiver pow er supply operating conditions could lead to unpredictable link behavior. (2) v cca_l/r must be connected to a 3.0-v supply if the clock multiplier uni t (cmu) phase-locked loop (pll), receiver clock data recovery ( cdr), or both, are configured at a base data rate > 4.25 gb ps. for data rates up to 4.25 gbps, you can connect v cca_l/r to either 3.0 v or 2.5 v. (3) n = 0, 1, 2, or 3. (4) v cch_gxbl/r must be connected to a 1.4-v su pply if the transmitter channel data rate is > 6.5 gbps. for data rates up to 6.5 gbps, you can connect v cch_gxbl/r to either 1.4 v or 1.5 v. table 1?8. transceiver power supply operating conditions for stratix iv gt devices (part 1 of 2) (1) , (2) symbol description minimum typical maximum unit v cca_l transceiver high voltage power (left side) 3.17 3.3 3.43 v v cca_r transceiver high voltage power (right side) 3.17 3.3 3.43 v v cchip_l transceiver hip digital power (left side) 0.92 0.95 0.98 v v cchip_r transceiver hip digital power (right side) 0.92 0.95 0.98 v v ccr_l receiver power (left side) 1.15 1.2 1.25 v chapter 1: dc and switching characteristics for stratix iv devices 1?7 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum dc characteristics this section lists the supply current, i/o pin leakage current, bus hold, on-chip termination (oct) tolerance, input pin capa citance, and hot socketing specifications. supply current standby current is the current drawn from the respective power rails used for power budgeting. use the excel-based early powe r estimator (epe) to get supply current estimates for your design because these currents vary greatly with the resources you use. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in the quartus ii handbook. i/o pin leakage current table 1?9 lists the stratix iv i/o pin leakage current specifications. v ccr_r receiver power (right side) 1.15 1.2 1.25 v v cct_l transmitter power (left side) 1.15 1.2 1.25 v v cct_r transmitter power (right side) 1.15 1.2 1.25 v v ccl_gxbln (3) transceiver clock power (left side) 1.15 1.2 1.25 v v ccl_gxbrn (3) transceiver clock power (right side) 1.15 1.2 1.25 v v cch_gxbln (3) transmitter output buffer power (left side) 1.33 1.4 1.47 v v cch_gxbrn (3) transmitter output buffer power (right side) 1.33 1.4 1.47 v notes to table 1?8 : (1) for the recommended operating conditions for stratix iv gt e ngineering sample (es1) devices, contact your local altera sales representative. (2) transceiver power supplies do not have power-on-reset circuitry. after initial powe r-up, violating the tr ansceiver power sup ply operating conditions could lead to unpredictable link behavior. (3) n = 0, 1, 2, or 3. table 1?8. transceiver power supply operating conditions for stratix iv gt devices (part 2 of 2) (1) , (2) symbol description minimum typical maximum unit table 1?9. i/o pin leakage current for stratix iv devices (1) symbol description conditions min typ max unit i i input pin v i = 0v to v cciomax -20 ? 20 a i oz tri-stated i/o pin v o = 0v to v cciomax -20 ? 20 a note to table 1?9 : (1) v ref current refers to the input pin leakage current. chapter 1: dc and switching characteristics for stratix iv devices 1?8 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum bus hold specifications table 1?10 lists the stratix iv device family bus hold specifications. on-chip termination (oct) specifications if you enable oct calibration, calibration is automatically performed at power-up for i/os connected to the calibration block. table 1?11 lists the stratix iv oct termination calibration accuracy specifications. table 1?10. bus hold parameters parameter symbol conditions v ccio unit 1.2 v 1.5 v 1.8 v 2.5 v 3.0 v min max min max min max min max min max low sustaining current i susl v in > v il (maximum) 22.5 ? 25.0 ? 30.0 ? 50.0 ? 70.0 ? a high sustaining current i sush v in < v ih (minimum) -22.5 ? -25.0 ? -30.0 ? -50.0 ? -70.0 ? a low overdrive current i odl 0v < v in < v ccio ? 120 ? 160 ? 200 ? 300 ? 500 a high overdrive current i odh 0v < v in < v ccio ?-120?-160?-200?-300?-500a bus-hold trip point v trip ? 0.450.950.501.000.681.070.701.700.802.00 v table 1?11. oct calibration accuracy specifications for stratix iv devices (part 1 of 2) (1) symbol description conditions calibration accuracy unit c2 c3,i3, m3 c4,i4 25- ? r s (2) 3.0, 2.5, 1.8, 1.5, 1.2 internal series termination with calibration (25- ? setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 v 8 8 8 % 50- ? r s 3.0, 2.5, 1.8, 1.5, 1.2 internal series termination with calibration (50- ? setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 v 8 8 8 % 50- ? r t 2.5, 1.8, 1.5, 1.2 internal parallel termination with calibration (50- ? setting) v ccio = 2.5, 1.8, 1.5, 1.2 v 10 10 10 % 20- ? , 40- ? , and 60- ? r s (3) 3.0, 2.5, 1.8, 1.5, 1.2 expanded range for internal series termination with calibration (20- ? , 40- ??? and 60- ? r s setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 v 10 10 10 % chapter 1: dc and switching characteristics for stratix iv devices 1?9 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum the calibration accuracy for ca librated series and parallel octs are applicable at the moment of calibration. when process, vo ltage, and temperature (pvt) conditions change after calibration, the tolerance may change. table 1?12 lists the stratix iv oct without calibration resistance tolerance to pvt changes. 25- ? r s_left_shift 3.0, 2.5, 1.8, 1.5, 1.2 internal left shift series termination with calibration (25- ? r s_left_shift setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 v 10 10 10 % notes to table 1?11 : (1) oct calibration accuracy is valid at the time of calibration only. (2) 25- ? r s is not supported for 1.5 v and 1.2 v in row i/o. (3) 20- ? r s is not supported for 1.5 v and 1.2 v in row i/o. table 1?11. oct calibration accuracy specifications for stratix iv devices (part 2 of 2) (1) symbol description conditions calibration accuracy unit c2 c3,i3, m3 c4,i4 table 1?12. oct without calibration resistance tolerance specifications for stratix iv devices symbol description conditions resistance tolerance unit c2 c3,i3, m3 c4,i4 25- ? r s 3.0 and 2.5 internal series termination without calibration (25- ? setting) v ccio = 3.0 and 2.5 v 30 40 40 % 25- ? r s 1.8 and 1.5 internal series termination without calibration (25- ? setting) v ccio = 1.8 and 1.5 v 30 40 40 % 25- ? r s 1.2 internal series termination without calibration (25- ? setting) v ccio = 1.2 v 35 50 50 % 50- ? r s 3.0 and 2.5 internal series termination without calibration (50- ? setting) v ccio = 3.0 and 2.5 v 30 40 40 % 50- ? r s 1.8 and 1.5 internal series termination without calibration (50- ? setting) v ccio = 1.8 and 1.5 v 30 40 40 % 50- ? r s 1.2 internal series termination without calibration (50- ? setting) v ccio = 1.2 v 35 50 50 % 100- ? r d 2.5 internal differential termination (100- ? setting) v ccio = 2.5 v 25 25 25 % chapter 1: dc and switching characteristics for stratix iv devices 1?10 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum oct calibration is automatically performed at power-up for oct-enabled i/os. table 1?13 lists oct variation with temperature and voltage after power-up calibration. use table 1?13 to determine the oct variation after power-up calibration and equation 1?1 to determine the oct variation without re-calibration. table 1?13 lists the oct variation after the power-up calibration. pin capacitance table 1?14 lists the stratix iv device family pin capacitance. equation 1?1. oct variation without re-calibration (1) , (2) , (3) , (4) , (5) , (6) notes to equation 1?1 : (1) the r oct value calculated from equation 1?1 shows the range of oct resistance with the variation of temperature and v ccio . (2) r scal is the oct resistance value at power-up. (3) ? t is the variation of temperature with respect to the temperature at power-up. (4) ? v is the variation of voltage with respect to the v ccio at power-up. (5) dr/dt is the percentage change of r scal with temperature. (6) dr/dv is the percentage change of r scal with voltage. table 1?13. oct variation after power-up calibration (1) symbol description v ccio (v) typical unit dr/dv oct variation with voltage without re-calibration 3.0 0.0297 %/mv 2.5 0.0344 1.8 0.0499 1.5 0.0744 1.2 0.1241 dr/dt oct variation with temperature without re-calibration 3.0 0.189 %/c 2.5 0.208 1.8 0.266 1.5 0.273 1.2 0.317 note to table 1?13 : (1) valid for v ccio range of 5% and temperature range of 0 to 85c. r oct r scal 1 dr dt ------ - ? ? ?? ------- ? ? ?? ? + ?? ?? = table 1?14. pin capacitance for stratix iv devices (part 1 of 2) symbol description value unit c iotb input capacitance on the top and bottom i/o pins 4 pf c iolr input capacitance on the left and right i/o pins 4 pf c clktb input capacitance on the top and bottom non-dedicated clock input pins 4 pf c clklr input capacitance on the left and right non-dedicated clock input pins 4 pf chapter 1: dc and switching characteristics for stratix iv devices 1?11 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum hot socketing table 1?15 lists the hot socketing specifications for stratix iv devices. internal weak pull-up resistor table 1?16 lists the weak pull-up resistor values for stratix iv devices. c outfb input capacitance on the dual-purpose clock output and feedback pins 5 pf c clk1 , c clk3 , c clk8 , and c clk10 input capacitance for dedicated clock input pins 2 pf table 1?14. pin capacitance for stratix iv devices (part 2 of 2) symbol description value unit table 1?15. hot socketing specifications for stratix iv devices symbol description maximum i iopin (dc) dc current per i/o pin 300 ? a i iopin (ac) ac current per i/o pin 8 ma (1) i xcvr-tx (dc) dc current per transceiver tx pin 100 ma i xcvr-rx (dc) dc current per transceiver rx pin 50 ma note to table 1?15 : (1) the i/o ramp rate is 10 ns or more. for ramp rates faster than 10 ns, |i iopin | = c dv/dt, in which c is the i/o pin capacitance and dv/dt is the slew rate. table 1?16. internal weak pull-up resistor for stratix iv devices (1) , (3) symbol description conditions (v) value (4) unit r pu value of the i/o pin pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled. v ccio = 3.0 5% (2) 25 k ? v ccio = 2.5 5% (2) 25 k ? v ccio = 1.8 5% (2) 25 k ? v ccio = 1.5 5% (2) 25 k ? v ccio = 1.2 5% (2) 25 k ? notes to table 1?16 : (1) all i/o pins have an option to enable weak pul l-up except configuration, test, and jtag pins. (2) pin pull-up resistance values may be lower if an external so urce drives the pin higher than v ccio . (3) the internal weak pull-down feature is only available for the jtag tck pin. the typical value for this in ternal weak pull-down resistor is approximately 25 k ?? (4) these specifications are valid with 10% tolerances to cover changes over pvt. chapter 1: dc and switching characteristics for stratix iv devices 1?12 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum i/o standard specifications table 1?17 through table 1?22 list the input voltage (v ih and v il ), output voltage (v oh and v ol ), and current drive characteristics (i oh and i ol ) for various i/o standards supported by stratix iv devices. these tables also show the stratix iv device family i/o standard specifications. v ol and v oh values are valid at the corresponding i oh and i ol , respectively. for an explanation of terms used in table 1?17 through table 1?22 , refer to ?glossary? on page 1?64 . table 1?17. single-ended i/o standards i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min typ max min max min max max min lvttl 2.85 3 3.15 -0.3 0.8 1.7 3.6 0.4 2.4 2 -2 lvcmos 2.85 3 3.15 -0.3 0.8 1.7 3.6 0.2 v ccio - 0.2 0.1 -0.1 2.5 v 2.375 2.5 2.625 -0.3 0.7 1.7 3.6 0.4 2 1 -1 1.8 v 1.71 1.8 1.89 -0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.45 v ccio - 0.45 2-2 1.5 v 1.425 1.5 1.575 -0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.25 * v ccio 0.75 * v ccio 2-2 1.2 v 1.14 1.2 1.26 -0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.25 * v ccio 0.75 * v ccio 2-2 3.0-v pci 2.85 3 3.15 ? 0.3 * v ccio 0.5 * v ccio 3.6 0.1 * v ccio 0.9 * v ccio 1.5 -0.5 3.0-v pci-x 2.85 3 3.15 ? 0.35 * v ccio 0.5 * v ccio ? 0.1 * v ccio 0.9 * v ccio 1.5 -0.5 table 1?18. single-ended sstl and hstl i/o reference voltage specifications i/o standard v ccio (v) v ref (v) v tt (v) min typ max min typ max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio v ref - 0.04 v ref v ref + 0.04 sstl-18 class i, ii 1.71 1.8 1.89 0.833 0.9 0.969 v ref - 0.04 v ref v ref + 0.04 sstl-15 class i, ii 1.425 1.5 1.575 0.47 * v ccio 0.5 * v ccio 0.53 * v ccio 0.47 * v ccio v ref 0.53 * v ccio hstl-18 class i, ii 1.71 1.8 1.89 0.85 0.9 0.95 ? v ccio /2 ? hstl-15 class i, ii 1.425 1.5 1.575 0.68 0.75 0.9 ? v ccio /2 ? hstl-12 class i, ii 1.14 1.2 1.26 0.47 * v ccio 0.5 * v ccio 0.53 * v ccio ?v ccio /2 ? chapter 1: dc and switching characteristics for stratix iv devices 1?13 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum table 1?19. single-ended sstl and hstl i/o standards signal specifications i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min sstl-2 class i -0.3 v ref - 0.15 v ref + 0.15 v ccio + 0.3 v ref - 0.31 v ref + 0.31 v tt - 0.57 v tt + 0.57 8.1 -8.1 sstl-2 class ii -0.3 v ref - 0.15 v ref + 0.15 v ccio + 0.3 v ref - 0.31 v ref + 0.31 v tt - 0.76 v tt + 0.76 16.2 -16.2 sstl-18 class i -0.3 v ref - 0.125 v ref + 0.125 v ccio + 0.3 v ref - 0.25 v ref + 0.25 v tt - 0.475 v tt + 0.475 6.7 -6.7 sstl-18 class ii -0.3 v ref - 0.125 v ref + 0.125 v ccio + 0.3 v ref - 0.25 v ref + 0.25 0.28 v ccio - 0.28 13.4 -13.4 sstl-15 class i ? v ref - 0.1 v ref + 0.1 ? v ref - 0.175 v ref + 0.175 0.2 * v ccio 0.8 * v ccio 8-8 sstl-15 class ii ? v ref - 0.1 v ref + 0.1 ? v ref - 0.175 v ref + 0.175 0.2 * v ccio 0.8 * v ccio 16 -16 hstl-18 class i ?v ref -0.1 v ref + 0.1 ? v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 8-8 hstl-18 class ii ? v ref - 0.1 v ref + 0.1 ? v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 16 -16 hstl-15 class i ? v ref - 0.1 v ref + 0.1 ? v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 8-8 hstl-15 class ii ? v ref - 0.1 v ref + 0.1 ? v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 16 -16 hstl-12 class i -0.15 v ref - 0.08 v ref + 0.08 v ccio + 0.15 v ref - 0.15 v ref + 0.15 0.25* v ccio 0.75* v ccio 8-8 hstl-12 class ii -0.15 v ref - 0.08 v ref + 0.08 v ccio + 0.15 v ref - 0.15 v ref + 0.15 0.25* v ccio 0.75* v ccio 16 -16 table 1?20. differential sstl i/o standards i/o standard v ccio (v) v swing(dc) (v) v x(ac) (v) v swing(ac) (v) v ox(ac) (v) min typ max min max min typ max min max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.3 v ccio + 0.6 v ccio /2 - 0.2 ? v ccio /2 + 0.2 0.62 v ccio + 0.6 v ccio /2 - 0.15 ? v ccio /2 + 0.15 sstl-18 class i, ii 1.71 1.8 1.89 0.25 v ccio + 0.6 v ccio /2 - 0.175 ? v ccio /2 + 0.175 0.5 v ccio + 0.6 v ccio /2 - 0.125 ? v ccio /2 + 0.125 sstl-15 class i, ii 1.425 1.5 1.575 0.2 ? ? v ccio /2 ? 0.35 ? ? v ccio /2 ? chapter 1: dc and switching characteristics for stratix iv devices 1?14 electrical characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum table 1?21. differential hstl i/o standards i/o standard v ccio (v) v dif(dc) (v) v x(ac) (v) v cm(dc) (v) v dif(ac) (v) min typ max min max min typ max min typ max min max hstl-18 class i 1.71 1.8 1.89 0.2 ? 0.78 ? 1.12 0.78 ? 1.12 0.4 ? hstl-15 class i, ii 1.425 1.5 1.575 0.2 ? 0.68 ? 0.9 0.68 ? 0.9 0.4 ? hstl-12 class i, ii 1.14 1.2 1.26 0.16 v ccio + 0.3 ? 0.5* v ccio ? 0.4* v ccio 0.5* v ccio 0.6* v ccio 0.3 v ccio + 0.48 table 1?22. differential i/o standard specifications (1) , (2) (part 1 of 2) i/o standard v ccio (v) (3) v id (mv) v icm(dc) (v) v od (v) (4) v ocm (v) (4) min typ max min condition max min condition max min typ max min typ max pcml transmitter, receiver, and input reference clock pins of high-speed transceivers use pcml i/o standard. for transmitter, receiver, and reference clock i/o pin specifications, refer to table 1?23 on page 1?16 and table 1?24 on page 1?25 . 2.5 v lvds (hio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 (5) d max ? 700 mbps 1.8 (5) 0.247 ? 0.6 1.125 1.25 1.375 ? 1.05 (5) d max > 700 mbps 1.55 ( 5) 0.247 ? 0.6 1.125 1.25 1.375 2.5 v lvds (vio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 d max ? 700 mbps 1.8 0.247 ? 0.6 1 1.25 1.5 ? 1.05 d max > 700 mbps 1.55 0.247 ? 0.6 1 1.25 1.5 rsds (hio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.3 ? 1.4 0.1 0.2 0.6 0.5 1.2 1.4 rsds (vio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.3 ? 1.4 0.1 0.2 0.6 0.5 1.2 1.5 mini-lvds (hio) 2.375 2.5 2.625 200 ? 600 0.4 ? 1.325 0.25 ? 0.6 1 1.2 1.4 mini-lvds (vio) 2.375 2.5 2.625 200 ? 600 0.4 ? 1.325 0.25 ? 0.6 1 1.2 1.5 lvpecl (7) 2.375 2.5 2.625 300 ? ? 0.6 (6) d max ? 700 mbps 1.8 (6) ??? ? ? ? 2.375 2.5 2.625 300 ? ? 1 (6) d max > 700 mbps 1.6 (6) ??? ? ? ? chapter 1: dc and switching characteristics for stratix iv devices 1?15 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum power consumption altera offers two ways to estimate powe r consumption for a design the excel-based early power estimator and the quartus ? ii powerplay power analyzer feature. 1 you typically use the interactive excel-based early power estimator before designing the fpga to get a magnitude estimate of the device power. the quartus ii powerplay power analyzer provides better quality esti mates based on the specifics of the design after you complete place-and-route. the powerplay power analyzer can apply a combination of user-entered, simulation-deriv ed, and estimated signal activities that, when combined with detailed circuit models , yields very accura te power estimates. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in the quartus ii handbook. switching characteristics this section provides performance characte ristics of stratix iv core and periphery blocks for commercial, industrial, and military grade devices. the final numbers are based on actual s ilicon characterization and testing. the numbers reflect the actual performance of th e device under worst-case silicon process, voltage, and junction temperature conditions . there are no designations on finalized tables. blvds (8) 2.375 2.5 2.625 100 ? ? ? ? ? ? ? ? ? ? ? notes to table 1?22 : (1) vertical i/o (vio) is top and bottom i/os; horizontal i/o (hio) is left and right i/os. (2) 1.4-v/1.5-v pcml transceiver i/o stan dard specifications are described in ?transceiver performance specifications? on page 1?16 . (3) differential clock inputs in column i/o are powered by v cc_clkin which requires 2.5 v. differential inputs that are not on clock pins in column i/o are powered by v ccpd which requires 2.5 v. all differential inputs in row i/o banks are powered by v ccpd which requires 2.5v. (4) rl range: 90 ? rl ? 110 ? . (5) the receiver voltage input ra nge for the data rate when d max > 700 mbps is 1.0 v ? v in ? 1.6 v. the receiver voltage input rang e for the data rate when d max ? 700 mbps is zero v ? v in ? 1.85 v. (6) the receiver voltage input ra nge for the data rate when d max > 700 mbps is 0.85 v ? v in ? 1.75 v. the receiver voltage input rang e for the data rate when d max ? 700 mbps is 0.45 v ? v in ? 1.95 v. (7) column and row i/o banks support lvpecl i/o standards for input operation only on dedicated clock input pins. (8) for more information about blvds interf ace support in altera devices, refer to an522: implementing bus lvds inte rfaces in supported altera device families . table 1?22. differential i/o standard specifications (1) , (2) (part 2 of 2) i/o standard v ccio (v) (3) v id (mv) v icm(dc) (v) v od (v) (4) v ocm (v) (4) min typ max min condition max min condition max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?16 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum transceiver performance specifications this section describes transceiver performance specifications. table 1?23 lists the stratix iv gx transceiver specifications. table 1?23. transceiver specifications for stratix iv gx devices (part 1 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade (1) ?3 military (2) and ?4 commercial/industrial speed grade unit min typ max min typ max min typ max reference clock supported i/o standards 1.2 v pcml, 1.4 v pcml 1.5 v pcml, 2.5 v pcml, differential lvpecl (4) , lvds, hcsl input frequency from refclk input pins ? 50 ? 697 50 ? 697 50 ? 637.5 mhz phase frequency detector (cmu pll and receiver cdr) ? 50 ? 425 50 ? 325 50 ? 325 mhz absolute v max for a refclk pin ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v operational v max for a refclk pin ? ? ? 1.5 ? ? 1.5 ? ? 1.5 v absolute v min for a refclk pin ? -0.4 ? ? -0.4 ? ? -0.4 ? ? v rise/fall time (21) ???0.2??0.2??0.2ui duty cycle ? 45 ? 55 45 ? 55 45 ? 55 % peak-to-peak differential input voltage ? 200 ? 1600 200 ? 1600 200 ? 1600 mv spread-spectrum modulating clock frequency pcie 30 ? 33 30 ? 33 30 ? 33 khz spread-spectrum downspread pcie ? 0 to -0.5% ?? 0 to -0.5% ?? 0 to -0.5% ?? on-chip termination resistors ? ? 100 ? ? 100 ? ? 100 ? ? v icm (ac coupled) ? 1100 10% 1100 10% 1100 10% mv v icm (dc coupled) hcsl i/o standard for pcie reference clock 250 ? 550 250 ? 550 250 ? 550 mv chapter 1: dc and switching characteristics for stratix iv devices 1?17 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum transmitter refclk phase noise 10 hz ? ? -50 ? ? -50 ? ? -50 dbc/hz 100 hz ? ? -80 ? ? -80 ? ? -80 dbc/hz 1 khz ? ? -110 ? ? -110 ? ? -110 dbc/hz 10 khz ? ? -120 ? ? -120 ? ? -120 dbc/hz 100 khz ? ? -120 ? ? -120 ? ? -120 dbc/hz ? 1 mhz ? ? -130 ? ? -130 ? ? -130 dbc/hz transmitter refclk phase jitter (rms) for 100 mhz refclk (3) 10 khz to 20 mhz ?? 3 ? ? 3 ? ? 3 ps r ref ?? 2000 1% ?? 2000 1% ?? 2000 1% ? ? transceiver clocks calibration block clock frequency ? 10 ? 125 10 ? 125 10 ? 125 mhz fixedclk clock frequency pcie receiver detect ? 125 ? ? 125 ? ? 125 ? mhz reconfig_clk clock frequency dynamic reconfiguration clock frequency 2.5/ 37.5 (5) ?50 2.5/ 37.5 (5) ?50 2.5/ 37.5 (5) ?50? delta time between reconfig_clks (19) ???2??2??2ms transceiver block minimum power-down ( gxb_powerdown ) pulse width ?1??1??1??s receiver supported i/o standards 1.4 v pcml, 1.5 v pcml, 2.5 v pcml, lvpecl, lvds data rate (single width, non-pma direct) (23) ? 600 ? 3750 600 ? 3750 600 ? 3750 mbps data rate (double width, non-pma direct) (23) ? 1000 ? 8500 1000 ? 6500 1000 ? 6375 (22) mbps data rate (single width, pma direct) (23) ? 600 ? 3250 600 ? 3250 600 ? 3250 mbps table 1?23. transceiver specifications for stratix iv gx devices (part 2 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade (1) ?3 military (2) and ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?18 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum data rate (double width, pma direct) (23) ? 1000 ? 6500 1000 ? 6500 1000 ? 6375 mbps absolute v max for a receiver pin (6) ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v operational v max for a receiver pin ? ? ? 1.5 ? ? 1.5 ? ? 1.5 v absolute v min for a receiver pin ? -0.4 ? ? -0.4 ? ? -0.4 ? ? v maximum peak-to-peak differential input voltage v id (diff p-p) before device configuration ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v maximum peak-to- peak differential input voltage v id (diff p-p) after device configuration v icm = 0.82 v setting ? ? 2.7 ? ? 2.7 ? ? 2.7 v v icm =1.1 v setting (7) ? ? 1.6 ? ? 1.6 ? ? 1.6 v minimum differential eye opening at receiver serial input pins (20) data rate = 600 mbps to 5 gbps equalization = 0 dc gain = 0 db 100 ? ? 100 ? ? 165 ? ? mv data rate >5gbps equalization = 0 dc gain = 0 db 165 ? ? 165 ? ? 165 ? ? mv v icm v icm = 0.82 v setting 820 10% 820 10% 820 10% mv v icm = 1.1 v setting (7) 1100 10% 1100 10% 1100 10% mv receiver dc coupling support ? for more information about receiver dc coupling support, refer to the ?dc- coupled links? section in the transceiver architecture in stratix iv devices chapter. differential on-chip termination resistors 85?? setting 85 20% 85 20% 85 20% ? 100?? setting 100 20% 100 20% 100 20% ? 120?? setting 120 20% 120 20% 120 20% ? 150- ? setting 150 20% 150 20% 150 20% ? table 1?23. transceiver specifications for stratix iv gx devices (part 3 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade (1) ?3 military (2) and ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?19 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum differential and common mode return loss pcie (gen 1 and gen 2), xaui, higig+, cei sr/lr, serial rapidio sr/lr, cpri lv/hv, obsai, sata compliant ? programmable ppm detector (8) ? 62.5, 100, 125, 200, 250, 300, 500, 1000 ppm run length ? ? ? 200 ? ? 200 ? ? 200 ui programmable equalization (18) ???16??16??16db t ltr (9) ???75??75??75s t ltr_ltd_manual (10) ?15??15??15??s t ltd_manual (11) ? ? ? 4000 ? ? 4000 ? ? 4000 ns t ltd_auto (12) ? 4000 ? ? 4000 ? ? 4000 ? ? ns receiver cdr 3 db bandwidth in lock-to-data (ltd) mode pcie gen1 20 - 35 mhz pcie gen2 40 - 65 mhz (oif) cei phy at 6.375 gbps 20 - 35 mhz xaui 10 - 18 mhz serial rapidio 1.25 gbps 10 - 18 mhz serial rapidio 2.5 gbps 10 - 18 mhz serial rapidio 3.125 gbps 6 - 10 mhz gige 6 - 10 mhz sonet oc12 3 - 6 mhz sonet oc48 14 - 19 mhz receiver buffer and cdr offset cancellation time (per channel) ??? 1850 0 ?? 1850 0 ? ? 18500 recon fig_ clk cycles table 1?23. transceiver specifications for stratix iv gx devices (part 4 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade (1) ?3 military (2) and ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?20 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum programmable dc gain dc gain setting = 0 ?0?? 0 ?? 0 ? db dc gain setting = 1 ?3?? 3 ?? 3 ? db dc gain setting = 2 ?6?? 6 ?? 6 ? db dc gain setting = 3 ?9?? 9 ?? 9 ? db dc gain setting = 4 ?12?? 12 ? ? 12 ? db eyeq data rate ? 600 ? 3250 600 ? 3250 600 ? 3250 mbps aeq data rate min v id (diff p-p) outer envelope = 600 mv 8b/10b encoded data 2500 ? 6500 2500 ? 6500 ? ? ? mbps decision feedback equalizer (dfe) data rate min v id (diff p-p) outer envelope = 500 mv 3125 ? 6500 3125 ? 6500 ? ? ? mbps transmitter supported i/o standards 1.4 v pcml, 1.5 v pcml data rate (single width, non-pma direct) ? 600 ? 3750 600 ? 3750 600 ? 3750 mbps data rate (double width, non-pma direct) ? 1000 ? 8500 1000 ? 6500 1000 ? 6375 (22) mbps data rate (single width, pma direct) ? 600 ? 3250 600 ? 3250 600 ? 3250 mbps data rate (double width, pma direct) (13) ? 1000 ? 6500 1000 ? 6500 1000 ? 6375 mbps v ocm 0.65 v setting ? 650 ? ? 650 ? ? 650 ? mv differential on-chip termination resistors 85?? setting 85 15% 85 15% 85 15% ? 100?? setting 100 15% 100 15% 100 15% ? 120?? setting 120 15% 120 15% 120 15% ? 150- ? setting 150 15% 150 15% 150 15% ? table 1?23. transceiver specifications for stratix iv gx devices (part 5 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade (1) ?3 military (2) and ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?21 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum differential and common mode return loss pcie gen1 and gen2 (tx v od =4), xaui (tx v od =6), higig+ (tx v od =6), cei sr/lr (tx v od =8), serial rapidio sr (v od =6), serial rapidio lr (v od =8), cpri lv (v od =6), cpri hv (v od =2), obsai (v od =6), sata (v od =4), compliant ? rise time (14) ? 50 ? 200 50 ? 200 50 ? 200 ps fall time (14) ? 50 ? 200 50 ? 200 50 ? 200 ps xaui rise time ? 60 ? 130 60 ? 130 60 ? 130 ps xaui fall time ? 60 ? 130 60 ? 130 60 ? 130 ps intra-differential pair skew ???15??15??15ps intra-transceiver block transmitter channel-to-channel skew 4 pma and pcs bonded mode example: xaui, pcie 4, basic 4 ? ? 120 ? ? 120 ? ? 120 ps inter-transceiver block transmitter channel-to-channel skew 8 pma and pcs bonded mode example: pcie 8, basic 8 ? ? 500 ? ? 500 ? ? 500 ps table 1?23. transceiver specifications for stratix iv gx devices (part 6 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade (1) ?3 military (2) and ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?22 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum inter-transceiver block skew in basic (pma direct) n mode (15) n < 18 channels located across three transceiver blocks with the source cmu pll located in the center transceiver block ? ? 400 ? ? 400 ? ? 400 ps n ? 18 channels located across four transceiver blocks with the source cmu pll located in one of the two center transceiver blocks ? ? 650 ? ? 650 ? ? 650 ps cmu0 pll and cmu1 pll supported data range ? 600 ? 8500 600 ? 6500 600 ? 6375 mbps pll_powerdown minimum pulse width ( tpll_powerdown ) ?1 ?s cmu pll lock time from pll_powerdown de-assertion ? ? ? 100 ? ? 100 ? ? 100 ?s table 1?23. transceiver specifications for stratix iv gx devices (part 7 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade (1) ?3 military (2) and ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?23 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum -3 db bandwidth pcie gen1 2.5 - 3.5 mhz pcie gen2 6 - 8 mhz (oif) cei phy at 4.976 gbps 7 - 11 mhz (oif) cei phy at 6.375 gbps 5 - 10 mhz xaui 2 - 4 mhz serial rapidio 1.25 gbps 3 - 5.5 mhz serial rapidio 2.5 gbps 3 - 5.5 mhz serial rapidio 3.125 gbps 2 - 4 mhz gige 2.5 - 4.5 mhz sonet oc12 1.5 - 2.5 mhz sonet oc48 3.5 - 6 mhz atx pll (6g) supported data range (16) /l = 1 4800-5400 and 6000-6500 4800-5400 and 6000-6500 4800-5400 and 6000-6375 mbps /l = 2 2400-2700 and 3000-3250 2400-2700 and 3000-3250 2400-2700 and 3000-3187.5 mbps /l = 4 1200-1350 and 1500-1625 1200-1350 and 1500-1625 1200-1350 and 1500-1593.75 mbps -3 db bandwidth pcie gen 2 1.5 1.5 ? mhz (oif) cei phy at 6.375 gbps 3 - 4.5 3 - 4.5 ? mhz transceiver-fpga fabric interface interface speed (non-pma direct) ? 25 ? 325 25 ? 325 25 ? 250 mhz interface speed (pma direct) ? 50 ? 325 50 ? 325 50 ? 325 mhz table 1?23. transceiver specifications for stratix iv gx devices (part 8 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade (1) ?3 military (2) and ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?24 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum digital reset pulse width ? minimum is two parallel clock cycles ? notes to table 1?23 : (1) the ? 2 speed grade is the fastest speed grad e offered in the following stratix iv gx devices: ep4sgx70df29, ep4sgx110df29, ep4sgx110ff35, ep4sgx230df29, ep4sgx 110ff35, ep4sgx180df29, ep4sgx230 ff35, ep4sgx290ff35, ep4sgx180ff35, ep4sgx290fh29, ep4sgx360ff35, and epsgx360fh29. (2) stratix iv gx devices in military speed grad e only support selected tran sceiver configuration up to 3125 mbps. for more informa tion, contact altera sales representative. (3) to calculate the refclk rms phase jitter requirement at reference clock frequencies other than 100 mhz, use the following for mula: refclk rms phase jitter at f (mhz) = refclk rms phase jitter at 100 mhz * 100/f. (4) differential lvpecl signal l evels must comply to the minimu m and maximum peak-to-peak differe ntial input voltage specified i n this table. (5) the minimum reconfig_clk frequency is 2.5 mhz if the tran sceiver channel is configured in transmitter only mode. the minimum reconfig_clk frequency is 37.5 mhz if the tran sceiver channel is configured in receiver only or receiver and transmitter mode. for more information, refer to the dynamic reconfiguration in stratix iv devices chapter. (6) the device cannot tolerate prolonged operation at this absolute maximum. (7) you must use the 1.1-v rx v icm setting if the input serial data standard is lvds. (8) the rate matcher supports only up to 300 parts per million (ppm). (9) time taken to rx_pll_locked goes high from rx_analogreset de-assertion. refer to figure 1?2 on page 1?33 . (10) time for which the cdr must be kept in lock-to-reference (ltr) mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. refer to figure 1?2 on page 1?33 . (11) time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. refer to figure 1?2 on page 1?33 . (12) time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. refer to figure 1?3 on page 1?33 . (13) a gpll may be required to meet the pma- fpga fabric interface timing above certain da ta rates. for more information, refer t o the ?left/right pll requirements in basic (pma direct) mode? section in the transceiver clocking in stratix iv devices chapter. (14) the quartus ii software automa tically selects the approp riate slew rate depending on the configured data rate or functional mode. (15) for applications that require low transmit lane-to-lane skew, use basic (pma direct) xn to achie ve pma-only bonding across all channels in the link. you can bond all channels on one side of the device by conf iguring them in basic (pma dir ect) xn mode. for more informati on about clocking requirements in this mo de, refer to the ?basic (pma dir ect) mode clocking? section in the transceiver clocking in stratix iv devices chapter. (16) the quartus ii software automatically selects the appropriate /l divider depending on the configured data. (17) the maximum transceiver-fpga fa bric interface speed of 265.625 mhz is allowed only in basic low-latency pcs mode with a 32-b it interface width. for more information, refer to the ?basic double-width mode configurations? section in the transceiver architecture in stratix iv devices chapter. (18) figure 1?1 shows the ac gain curves for each of the 16 available equalization settings. (19) if your design uses more than one dynamic reconfiguration controller ( altgx_reconfig ) instances to control the transceiver ( altgx ) channels physically located on the same side of the device and if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not excee d the maximum spec ification listed. (20) the differential eye openin g specification at the receiv er input pins assumes that receiver equalization is disabled. if you enable receiver equalization , the receiver circuitry can tolerate a lower minimum eye open ing, depending on the equalizati on level. use h-sp ice simulation to derive the minimum eye openi ng requirement with receiver equalization enabled. (21) the rise and fall time transiti on is specified from 20% to 80%. (22) stratix iv gx devices in -4 speed grade support basic mode and deterministic latency mode tr ansceiver configur ations up to 6375 mbps. these configurations are shown in the figures 1-90, 1-92, 1-94, 1-96, and 1-101 in the transceiver architecture in stratix iv devices chapter. (23) to support data rates lower than 600-mbps specificat ion through oversampling, use the cdr in ltr mode only. table 1?23. transceiver specifications for stratix iv gx devices (part 9 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade (1) ?3 military (2) and ?4 commercial/industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?25 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum figure 1?1 shows the top-to-bottom ac gain curv e for equalization settings 0 to 15. table 1?24 lists the stratix iv gt transceiver specifications. figure 1?1. ac gain curves for equalization settings 0 to 15 (bottom to top) table 1?24. transceiver specifications for stratix iv gt devices (part 1 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max reference clock supported i/o standards 1.2 v pcml, 1.4 v pcml, 1.5 v pcml, 2.5 v pcml, differential lvpecl (3) , lvds input frequency from refclk input pins ? 50 ? 706.25 50 ? 706.25 50 ? 706.25 mhz phase frequency detector (cmu pll and receiver cdr) ? 50 ? 425 50 ? 425 50 ? 425 mhz absolute v max for a refclk pin ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v operational v max for a refclk pin ? ? ? 1.5 ? ? 1.5 ? ? 1.5 v absolute v min for a refclk pin ? -0.3 ? ? -0.3 ? ? -0.3 ? ? v chapter 1: dc and switching characteristics for stratix iv devices 1?26 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum rise/fall time ? ? ? 0.2 ? ? 0.2 ? ? 0.2 ui duty cycle ? 45 ? 55 45 ? 55 45 ? 55 % peak-to-peak differential input voltage ? 200 ? 1200 200 ? 1200 200 ? 1200 mv on-chip termination resistors ? ? 100 ? ? 100 ? ? 100 ? ? v icm ? 1200 10% 1200 10% 1200 10% mv transmitter refclk phase noise 10 hz ? ? -50 ? ? -50 ? ? -50 dbc/hz 100 hz ? ? -80 ? ? -80 ? ? -80 dbc/hz 1 khz ? ? -110 ? ? -110 ? ? -110 dbc/hz 10 khz ? ? -120 ? ? -120 ? ? -120 dbc/hz 100 khz ? ? -120 ? ? -120 ? ? -120 dbc/hz ? 1 mhz ? ? -130 ? ? -130 ? ? -130 dbc/hz transmitter refclk phase jitter (rms) for 100 mhz refclk (2) 10 khz to 20 mhz ?? 3 ?? 3 ?? 3 ps r ref ??? 2000 1% ? 2000 1% ?? 2000 1% ? ? transceiver clocks calibration block clock frequency ? 10 ? 125 10 ? 125 10 ? 125 mhz reconfig_clk clock frequency dynamic reconfiguration clock frequency 2.5/ 37.5 (1) ?? 2.5/ 37.5 (1) ?50 2.5/ 37.5 (1) ?50 mhz fixedclk clock frequency pcie receiver detect ? 125 ? ? 125 ? ? 125 ? mhz delta time between reconfig_clks (15) ???2??2??2ms transceiver block minimum ( gxb_powerdown ) power-down pulse width ??1??1??1?s receiver supported i/o standards 1.4 v pcml, 1.5 v pcml, 2.5 v pcml, lvpecl, lvds data rate (single width, non-pma direct) (16) ? 600 ? 3750 600 ? 3750 600 ? 3750 mbps table 1?24. transceiver specifications for stratix iv gt devices (part 2 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?27 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum data rate (double width, non-pma direct) (16) ? 1000 ? 11300 1000 - 10312.5 1000 ? 8500 mbps data rate (single width, pma direct) (16) ? 600 - 3250 600 - 3250 600 ? 3250 mbps data rate (double width, pma direct) (16) ? 1000 - 6500 1000 - 6500 1000 ? 6500 mbps absolute v max for a receiver pin (4) ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v operational v max for a receiver pin ? ? ? 1.5 ? ? 1.5 ? ? 1.5 v absolute v min for a receiver pin ? ? -0.4 ? -0.4 ? ? -0.4 ? ? v maximum peak-to-peak differential input voltage v id (diff p-p) before device configuration ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v maximum peak-to-peak differential input voltage v id (diff p-p) after device configuration v icm = 0.82 v setting ??2.7?? 2.7 ?? 2.7 v v icm = 1.2 v setting (5) ??1.2?? 1.2 ?? 1.2 v minimum differential eye opening at the receiver serial input pins for data rates ? 10.3125 gbps. equalization = 0 (6) dc gain = 0 db 85 ? ? 85 ? ? 85 ? ? mv minimum differential eye opening at the receiver serial input pins for data rates > 10.3125 gbps. equalization = 0 (6) dc gain = 0 db 165 ? ? ? ? ? ? ? ? mv v icm v icm = 0.82 v setting 820 10% 820 10% 820 10% mv v icm = 1.2 v setting (5) 1200 10% 1200 10% 1200 10% mv table 1?24. transceiver specifications for stratix iv gt devices (part 3 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?28 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum differential on-chip termination resistors 85?? setting 85 20% 85 20% 85 20% ? 100 ?? setting 100 20% 100 20% 100 20% ? 120 ?? setting 120 20% 120 20% 120 20% ? 150- ? setting 150 20% 150 20% 150 20% ? differential and common mode return loss pcie (gen 1 and gen 2), xaui, higig+, cei sr/lr, serial rapidio sr/lr, cpri lv/hv, obsai, sata compliant ? programmable ppm detector (7) ?? 62.5, 100, 125, 200, 250, 300, 500, 1000 ppm run length ? ? ? 200 ? ? 200 ? ? 200 ui programmable equalization ???16??16??16db t ltr (8) ???75??75??75s t ltr_ltd_manual (9) ?15??15??15??s t ltd_manual (10) ? ? ? 4000 ? ? 4000 ? ? 4000 ns t ltd_auto (11) ? 4000 ? ? 4000 ? ? 4000 ? ? ns receiver buffer and cdr offset cancellation time (per channel) ? ? ? 17000 ? ? 17000 ? ? 17000 reconfig_clk cycles programmable dc gain dc gain setting = 0 ?0??0 ? ?0 ? db dc gain setting = 1 ?3??3 ? ?3 ? db dc gain setting = 2 ?6??6 ? ?6 ? db dc gain setting = 3 ?9??9 ? ?9 ? db dc gain setting = 4 ?12? ?12 ? ?12 ? db eyeq max data rate ? ? ? 4.0 ? ? 4.0 ? ? 4.0 gbps table 1?24. transceiver specifications for stratix iv gt devices (part 4 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?29 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum aeq data rate min v id (diff p-p) outer envelope = 600 mv 8b/10b encoded data 2500 ? 6500 2500 ? 6500 ? ? ? mbps decision feedback equalizer (dfe) data rate min v id (diff p-p) outer envelope = 600 mv 3125 ? 6500 3125 ? 6500 ? ? ? mbps transmitter supported i/o standards 1.4 v pcml data rate (single width, non-pma direct) ? 600 ? 3750 600 ? 3750 600 ? 3750 mbps data rate (double width, non-pma direct) ? 1000 ? 11300 1000 ? 10312.5 1000 ? 8500 mbps data rate (single width, pma direct) ? 600 ? 3250 600 ? 3250 600 ? 3250 mbps data rate (double width, pma direct) (12) ? 1000 ? 6500 1000 ? 6500 1000 ? 6500 mbps v ocm 0.65 v setting ? 650 ? ? 650 ? ? 650 ? mv differential on-chip termination resistors 85?? setting 85 15% 85 15% 85 15% ? 100 ?? setting 100 15% 100 15% 100 15% ? 120 ?? setting 120 15% 120 15% 120 15% ? 150- ? setting 150 15% 150 15% 150 15% ? table 1?24. transceiver specifications for stratix iv gt devices (part 5 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?30 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum differential and common mode return loss pcie gen1 and gen2 (tx v od =4), xaui (tx v od =6), higig+ (tx v od =6), cei sr/lr (tx v od =8), serial rapidio sr (v od =6), serial rapidio lr (v od =8), cpri lv (v od =6), cpri hv (v od =2), obsai (v od =6), sata (v od =4), compliant ? rise time (13) ? 50 ? 200 50 ? 200 50 ? 200 ps fall time (13) ? 50 ? 200 50 ? 200 50 ? 200 ps xaui rise time ? 60 ? 130 60 ? 130 60 ? 130 ps xaui fall time ? 60 ? 130 60 ? 130 60 ? 130 ps intra-differential pair skew ???15??15??15ps intra-transceiver block transmitter channel-to-channel skew 4 pma and pcs bonded mode example: xaui, pcie, 4, basic 4 ? ? 120 ? ? 120 ? ? 120 ps inter-transceiver block transmitter channel-to-channel skew 8 pma and pcs bonded mode example: pcie 8, basic 8 ? ? 500 ? ? 500 ? ? 500 ps table 1?24. transceiver specifications for stratix iv gt devices (part 6 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?31 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum inter-transceiver block skew in basic (pma direct) n mode (14) n < 18 channels located across three transceiver blocks with the source cmu pll located in the center transceiver block ? ? 400 ? ? 400 ? ? 400 ps n ? 18 channels located across four transceiver blocks with the source cmu pll located in one of the two center transceiver blocks ? ? 650 ? ? 650 ? ? 650 ps cmu pll0 and cmu pll1 supported data range ? 600 ? 11300 600 ? 10312.5 600 ? 8500 mbps cmu pll lock time from pll_powerdown de-assertion ? ? ? 100 ? ? 100 ? ? 100 ?s atx pll (6g) supported data range /l = 1 4800-5400 and 6000-6500 4800-5400 and 6000-6500 4800-5400 and 6000-6500 mbps /l = 2 2400-2700 and 3000-3250 2400-2700 and 3000-3250 2400-2700 and 3000-3250 mbps /l = 4 1200-1350 and 1500-1625 1200-1350 and 1500-1625 1200-1350 and 1500-1625 mbps atx pll (10g) supported data range ? 9900 ? 11300 9900 ? 10312.5 ? mbps transceiver-fpga fabric interface interface speed (non-pma direct) ? 25 ? 325 25 ? 325 25 ? 265.625 mhz interface speed (pma direct) ? 50 ? 325 50 ? 325 50 ? 325 mhz table 1?24. transceiver specifications for stratix iv gt devices (part 7 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?32 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum digital reset pulse width ? minimum is two parallel clock cycles ? notes to table 1?24 : (1) the minimum reconfig_clk frequency is 2.5 mhz if the tran sceiver channel is configured in transmitter only mode. the minimum reconfig_clk frequency is 37.5 mhz if the transce iver channel is configured in receiver only or receiver and transmitter mode. for more inform ation, refer to the dynamic reconfiguration in stratix iv devices chapter. (2) to calculate the refclk rms phase jitter requirement at reference clo ck frequencies other than 10 0 mhz, use the following for mula: refclk rms phase jitter at f (mhz) = refclk rm s phase jitter at 100 mhz * 100/f. (3) differential lvpecl signal l evels must comply to the minimu m and maximum peak-to-peak differe ntial input voltage specified i n this table. (4) the device cannot tolerate prolonged operation at this absolute maximum. (5) you must use the 1.2-v rxv icm setting if the input seria l data standard is lvds. (6) the differential eye opening specification at the receiver inpu t pins assumes that receiver equalization is disabled. if you enable receiver equalization , the receiver circuitry can tolerate a lo wer minimum eye opening, depe nding on the equali zation level. use h-spice simulation to derive the minimum eye opening requirement with receiver equalization enabled. (7) the rate matcher supports only up to 300 ppm. (8) time taken to rx_pll_locked goes high from rx_analogreset de-assertion. refer to figure 1?2 on page 1?33 . (9) time for which the cdr must be kep t in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. refer to figure 1?2 on page 1?33 . (10) time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. refer to figure 1?2 on page 1?33 . (11) time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. refer to figure 1?3 on page 1?33 . (12) a gpll may be required to meet the pm a-fpga fabric interface timing above certain da ta rates. for more information, refer t o the ?left/right pll requirements in basic (pma direct) mode? section in the transceiver clocking in stratix iv devices chapter. (13) the quartus ii software automa tically selects the approp riate slew rate depending on the configured data rate or functional mode. (14) for applications that require low tran smit lane-to-lane skew, use basic (pma di rect) xn to achieve pma-only bonding across all channels in the link. you can bond all channels on one side of the device by configurin g them in basic (pma direct) xn mode. for more information abo ut clocking requirements in this mode, refer to the ?basi c (pma direct) mode clocking? section in the transceiver clocking in stratix iv devices chapter. (15) if your design uses more than one dynamic reconfiguration controller ( altgx_reconfig ) instances to control the transceiver ( altgx ) channels physically located on the same side of the device and if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not excee d the maximum spec ification listed. (16) to support data rates lower than 600-mbps specificat ion through oversampling, use the cdr in ltr mode only. table 1?24. transceiver specifications for stratix iv gt devices (part 8 of 8) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?33 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum figure 1?2 shows the lock time parameters in manual mode. 1 ltd = lock-to-data; ltr = lock-to-reference figure 1?3 shows the lock time para meters in automatic mode. figure 1?2. lock time parameters for manual mode ltr ltd invalid data valid data r x_locktodata ltd_manual cdr status r x_dataout r x_pl l_locked r x_analogreset ltr ltr_ltd_manual t t t figure 1?3. lock time parameters for automatic mode ltr ltd invalid data valid data r x_freqlocked ltd_auto r x_dataout cdr status t chapter 1: dc and switching characteristics for stratix iv devices 1?34 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum table 1?25 through table 1?28 lists the typical differential v od termination settings for stratix iv gx and gt devices. table 1?29 lists typical transmitter pre-emphasis levels in db for the first post tap under the following conditions (low-frequency data pattern [five 1s and five 0s] at 6.25 gbps). the levels listed in table 1?29 are a representation of possible pre-emphasis levels under the specified conditions only and that the pre-emphasis levels may change with data pattern and data rate. f to predict the pre-emphasis level for your specific data rate and pattern, run simulations using the stratix iv hssi hspice models. table 1?25. typical v od setting, tx term = 85 ? symbol v od setting (mv) 01234567 v od differential peak-to-peak typical (mv) 170 20% 340 20% 510 20% 595 20% 680 20% 765 20% 850 20% 1020 20% table 1?26. typical v od setting, tx term = 100 ? symbol v od setting (mv) 01234567 v od differential peak-to-peak typical (mv) 200 20% 400 20% 600 20% 700 20% 800 20% 900 20% 1000 20% 1200 20% table 1?27. typical v od setting, tx term = 120 ? symbol v od setting (mv) 0123456 v od differential peak-to-peak typical (mv) 240 20% 480 20% 720 20% 840 20% 960 20% 1080 20% 1200 20% table 1?28. typical v od setting, tx term = 150 ? symbol v od setting (mv) 012345 v od differential peak-to-peak typical (mv) 300 20% 600 20% 900 20% 1050 20% 1200 20% 1350 20% table 1?29. transmitter pre-emphasis levels for stratix iv devices (part 1 of 2) pre-emphasis 1st post-tap setting v od setting 01234567 0 00000000 1 n/a0.7000000 2 n/a10.300000 3 n/a1.50.600000 chapter 1: dc and switching characteristics for stratix iv devices 1?35 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum 4 n/a20.70.30000 5 n/a 2.7 1.2 0.5 0.3 0 0 0 6 n/a 3.1 1.3 0.8 0.5 0.2 0 0 7 n/a 3.7 1.8 1.1 0.7 0.4 0.2 0 8 n/a 4.2 2.1 1.3 0.9 0.6 0.3 0 9 n/a 4.9 2.4 1.6 1.2 0.8 0.5 0.2 10 n/a 5.4 2.8 1.9 1.4 1 0.7 0.3 11 n/a 6 3.2 2.2 1.7 1.2 0.9 0.4 12 n/a 6.8 3.5 2.6 1.9 1.4 1.1 0.6 13 n/a 7.5 3.8 2.8 2.1 1.6 1.2 0.6 14 n/a 8.1 4.2 3.1 2.3 1.7 1.3 0.7 15 n/a 8.8 4.5 3.4 2.6 1.9 1.5 0.8 16 n/a n/a 4.9 3.7 2.9 2.2 1.7 0.9 17 n/a n/a 5.3 4 3.1 2.4 1.8 1.1 18 n/a n/a 5.7 4.4 3.4 2.6 2 1.2 19 n/a n/a 6.1 4.7 3.6 2.8 2.2 1.4 20 n/a n/a 6.6 5.1 4 3.1 2.4 1.5 21 n/a n/a 7 5.4 4.3 3.3 2.7 1.7 22 n/a n/a 8 6.1 4.8 3.8 3 2 23 n/a n/a 9 6.8 5.4 4.3 3.4 2.3 24 n/a n/a 10 7.6 6 4.8 3.9 2.6 25 n/a n/a 11.4 8.4 6.8 5.4 4.4 3 26 n/a n/a 12.6 9.4 7.4 5.9 4.9 3.3 27 n/a n/a n/a 10.3 8.1 6.4 5.3 3.6 28 n/a n/a n/a 11.3 8.8 7.1 5.8 4 29 n/a n/a n/a 12.5 9.6 7.7 6.3 4.3 30 n/a n/a n/a n/a 11.4 9 7.4 n/a 31 n/a n/a n/a n/a 12.9 10 8.2 n/a table 1?29. transmitter pre-emphasis levels for stratix iv devices (part 2 of 2) pre-emphasis 1st post-tap setting v od setting 01234567 chapter 1: dc and switching characteristics for stratix iv devices 1?36 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum table 1?30 lists the stratix iv gx transceiver jitter specifications for all supported protocols. for protocols supported by strati x iv gt industrial speed grade devices, refer to the stratix iv gx ?2 commercial speed grade column in table 1?30 . table 1?30. transceiver block jitter specifications for stratix iv gx devices (1) , (2) (part 1 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?3 military (3) and ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max sonet/sdh transmit jitter generation (4) peak-to-peak jitter at 622.08 mbps pattern = prbs15 ? ? 0.1 ? ? 0.1 ? ? 0.1 ui rms jitter at 622.08 mbps pattern = prbs15 ? ? 0.01 ? ? 0.01 ? ? 0.01 ui peak-to-peak jitter at 2488.32 mbps pattern = prbs15 ? ? 0.1 ? ? 0.1 ? ? 0.1 ui rms jitter at 2488.32 mbps pattern = prbs15 ? ? 0.01 ? ? 0.01 ? ? 0.01 ui sonet/sdh receiver jitter tolerance (4) jitter tolerance at 622.08 mbps jitter frequency = 0.03 khz pattern = prbs15 > 15 > 15 > 15 ui jitter frequency = 25 khz pattern = prbs15 > 1.5 > 1.5 > 1.5 ui jitter frequency = 250 khz pattern = prbs15 > 0.15 > 0.15 > 0.15 ui jitter tolerance at 2488.32 mbps jitter frequency = 0.06 khz pattern = prbs15 > 15 > 15 > 15 ui jitter frequency = 100 khz pattern = prbs15 > 1.5 > 1.5 > 1.5 ui jitter frequency = 1 mhz pattern = prbs15 > 0.15 > 0.15 > 0.15 ui jitter frequency = 10 mhz pattern = prbs15 > 0.15 > 0.15 > 0.15 ui fibre channel transmit jitter generation (5) , (13) total jitter fc-1 pattern = crpat ? ? 0.23 ? ? 0.23 ? ? 0.23 ui deterministic jitter fc-1 pattern = crpat ? ? 0.11 ? ? 0.11 ? ? 0.11 ui total jitter fc-2 pattern = crpat ? ? 0.33 ? ? 0.33 ? ? 0.33 ui deterministic jitter fc-2 pattern = crpat ? ? 0.2 ? ? 0.2 ? ? 0.2 ui chapter 1: dc and switching characteristics for stratix iv devices 1?37 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum total jitter fc-4 pattern = crpat ? ? 0.52 ? ? 0.52 ? ? 0.52 ui deterministic jitter fc-4 pattern = crpat ? ? 0.33 ? ? 0.33 ? ? 0.33 ui fibre channel receiver jitter tolerance (5) , (14) deterministic jitter fc-1 pattern = cjtpat > 0.37 > 0.37 > 0.37 ui random jitter fc-1 pattern = cjtpat > 0.31 > 0.31 > 0.31 ui sinusoidal jitter fc-1 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui deterministic jitter fc-2 pattern = cjtpat > 0.33 > 0.33 > 0.33 ui random jitter fc-2 pattern = cjtpat > 0.29 > 0.29 > 0.29 ui sinusoidal jitter fc-2 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui deterministic jitter fc-4 pattern = cjtpat > 0.33 > 0.33 > 0.33 ui random jitter fc-4 pattern = cjtpat > 0.29 > 0.29 > 0.29 ui sinusoidal jitter fc-4 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui xaui transmit jitter generation (6) total jitter at 3.125 gbps pattern = cjpat ? ? 0.3 ? ? 0.3 ? ? 0.3 ui deterministic jitter at 3.125 gbps pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ui xaui receiver jitter tolerance (6) total jitter ? > 0.65 > 0.65 > 0.65 ui deterministic jitter ? > 0.37 > 0.37 > 0.37 ui peak-to-peak jitter jitter frequency = 22.1 khz > 8.5 > 8.5 > 8.5 ui peak-to-peak jitter jitter frequency = 1.875 mhz > 0.1 > 0.1 > 0.1 ui peak-to-peak jitter jitter frequency = 20 mhz > 0.1 > 0.1 > 0.1 ui pcie transmit jitter generation (7) total jitter at 2.5 gbps (gen1) compliance pattern ? ? 0.25 ? ? 0.25 ? ? 0.25 ui total jitter at 5 gbps (gen2) (15) compliance pattern ? ? 0.25 ? ? 0.25 ? ? ? ui pcie receiver jitter tolerance (7) total jitter at 2.5 gbps (gen1) compliance pattern > 0.6 > 0.6 > 0.6 ui table 1?30. transceiver block jitter specifications for stratix iv gx devices (1) , (2) (part 2 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?3 military (3) and ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?38 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum total jitter at 5 gbps (gen2) compliance pattern compliant compliant ? ui pcie (gen 1) electrical idle detect threshold v rx-idle-detdiffp-p (16) compliance pattern 65 ? 175 65 ? 175 65 ? 175 ui serial rapidio transmit jitter generation (8) deterministic jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ui total jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui serial rapidio receiver jitter tolerance (8) deterministic jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.55 > 0.55 > 0.55 ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1 khz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 1.875 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 > 0.1 > 0.1 ui jitter frequency = 20 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 > 0.1 > 0.1 ui gige transmit jitter generation (9) deterministic jitter (peak-to-peak) pattern = crpat ? ? 0.14 ? ? 0.14 ? ? 0.14 ui total jitter (peak-to-peak) pattern = crpat ? ? 0.279 ? ? 0.279 ? ? 0.279 ui table 1?30. transceiver block jitter specifications for stratix iv gx devices (1) , (2) (part 3 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?3 military (3) and ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?39 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum gige receiver jitter tolerance (9) deterministic jitter tolerance (peak-to-peak) pattern = cjpat > 0.4 > 0.4 > 0.4 ui combined deterministic and random jitter tolerance (peak-to-peak) pattern = cjpat > 0.66 > 0.66 > 0.66 ui higig transmit jitter generation (10) deterministic jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ? ? 0.17 ? ? ? ? ? ? ui total jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ? ? 0.35 ? ? ? ? ? ? ui higig receiver jitter tolerance (10) deterministic jitter tolerance (peak-to-peak) data rate = 3.75 gbps pattern = cjpat > 0.37 ? ? ? ? ? ? ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 3.75 gbps pattern = cjpat > 0.65 ? ? ? ? ? ? ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1 khz data rate = 3.75 gbps pattern = cjpat > 8.5 ? ? ? ? ? ? ui jitter frequency = 1.875mhz data rate = 3.75 gbps pattern = cjpat > 0.1 ? ? ? ? ? ? ui jitter frequency = 20 mhz data rate = 3.75 gbps pattern = cjpat > 0.1 ? ? ? ? ? ? ui (oif) cei transmitter jitter generation (11) total jitter (peak-to-peak) data rate = 6.375 gbps pattern = prbs15 ber = 10 -12 ? ? 0.3 ? ? 0.3 ? ? 0.3 ui (oif) cei receiver jitter tolerance (11) deterministic jitter tolerance (peak-to-peak) data rate = 6.375 gbps pattern = prbs31 ber = 10 -12 > 0.675 > 0.675 ? ? >0.675 ui table 1?30. transceiver block jitter specifications for stratix iv gx devices (1) , (2) (part 4 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?3 military (3) and ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max 1?40 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum combined deterministic and random jitter tolerance (peak-to-peak) data rate = 6.375 gbps pattern=prbs31 ber = 10 -12 > 0.988 > 0.988 ? ? >0.988 ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 38.2 khz data rate = 6.375 gbps pattern = prbs31 ber = 10 -12 > 5 > 5 ? ? > 5 ui jitter frequency = 3.82 mhz data rate = 6.375 gbps pattern = prbs31 ber = 10 -12 > 0.05 > 0.05 ? ? > 0.05 ui jitter frequency = 20 mhz data rate= 6.375 gbps pattern = prbs31 ber = 10 -12 > 0.05 > 0.05 ? ? > 0.05 ui sdi transmitter jitter generation (12) alignment jitter (peak-to-peak) data rate = 1.485 gbps (hd) pattern = color bar low-frequency roll-off = 100 khz 0.2 ? ? 0.2 ? ? 0.2 ? ? ui data rate = 2.97 gbps (3g) pattern = color bar low-frequency roll-off = 100 khz 0.3 ? ? 0.3 ? ? 0.3 ? ? ui table 1?30. transceiver block jitter specifications for stratix iv gx devices (1) , (2) (part 5 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?3 military (3) and ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?41 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum sdi receiver jitter tolerance (12) sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 15 khz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 2 > 2 > 2 ui jitter frequency = 100 khz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 0.3 > 0.3 > 0.3 ui jitter frequency = 148.5 mhz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 0.3 > 0.3 > 0.3 ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 20 khz data rate = 1.485 gbps (hd) pattern = 75% color bar > 1 > 1 > 1 ui jitter frequency = 100 khz data rate = 1.485 gbps (hd) pattern = 75% color bar > 0.2 > 0.2 > 0.2 ui jitter frequency = 148.5 mhz data rate = 1.485 gbps (hd) pattern = 75% color bar > 0.2 > 0.2 > 0.2 ui sas transmit jitter generation (17) total jitter at 1.5 gbps (g1) pattern = cjpat ? ? 0.55 ? ? 0.55 ? ? 0.55 ui deterministic jitter at 1.5 gbps (g1) pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui total jitter at 3.0 gbps (g2) pattern = cjpat ? ? 0.55 ? ? 0.55 ? ? 0.55 ui deterministic jitter at 3.0 gbps (g2) pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui total jitter at 6.0 gbps (g3) pattern = cjpat ? ? 0.25 ? ? 0.25 ? ? 0.25 ui table 1?30. transceiver block jitter specifications for stratix iv gx devices (1) , (2) (part 6 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?3 military (3) and ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max 1?42 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum random jitter at 6.0 gbps (g3) pattern = cjpat ? ? 0.15 ? ? 0.15 ? ? 0.15 ui sas receiver jitter tolerance (17) total jitter tolerance at 1.5 gbps (g1) pattern = cjpat > 0.65 > 0.65 > 0.65 ui deterministic jitter tolerance at 1.5 gbps (g1) pattern = cjpat > 0.35 > 0.35 > 0.35 ui sinusoidal jitter tolerance at 1.5 gbps (g1) jitter frequency = 900 khz to 5 mhz pattern = cjtpat ber = 1e-12 > 0.1 > 0.1 > 0.1 ui cpri transmit jitter generation (18) total jitter e.6.hv, e.12.hv pattern = cjpat ? ? 0.279 ? ? 0.279 ? ? 0.279 ui e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui deterministic jitter e.6.hv, e.12.hv pattern = cjpat ? ? 0.14 ? ? 0.14 ? ? 0.14 ui e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ui cpri receiver jitter tolerance (18) total jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.66 > 0.66 > 0.66 ui deterministic jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.4 > 0.4 > 0.4 ui total jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.65 > 0.65 > 0.65 ui deterministic jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.55 > 0.55 > 0.55 ui table 1?30. transceiver block jitter specifications for stratix iv gx devices (1) , (2) (part 7 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?3 military (3) and ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?43 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum obsai transmit jitter generation (19) total jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6mhz pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui deterministic jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6mhz pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ui obsai receiver jitter tolerance (19) deterministic jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.55 > 0.55 > 0.55 ui sinusoidal jitter tolerance at 768 mbps jitter frequency = 5.4 khz pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 460 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 ui sinusoidal jitter tolerance at 1536 mbps jitter frequency = 10.9 khz pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 921.6 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 ui table 1?30. transceiver block jitter specifications for stratix iv gx devices (1) , (2) (part 8 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?3 military (3) and ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max 1?44 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum sinusoidal jitter tolerance at 3072 mbps jitter frequency = 21.8 khz pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 1843.2 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 ui notes to table 1?30 : (1) dedicated refclk pins were used to dri ve the input reference clocks. (2) the jitter numbers are valid fo r the stated co nditions only. (3) stratix iv gx devices in military speed gr ade only support selected transceiver confi guration up to 3125 mbps . for more informa tion, contact altera sales representative. (4) the jitter numbers for sonet/sdh are compli ant to the gr-253-core issue 3 specification. (5) the jitter numbers for fibre ch annel are compliant to the fc-pi-4 specification revision 6.10. (6) the jitter numbers for xaui are compli ant to the ieee802.3ae-2002 specification. (7) the jitter numbers for pci express (pipe) (pcie) are compliant to the pci e base specification 2.0. (8) the jitter numbers for serial rapidio are compliant to the rapi dio specification 1.3. (9) the jitter numbers for gige are compli ant to the ieee802.3-2002 specification. (10) the jitter numbers for higig are compli ant to the ieee802.3ae-2002 specification. (11) the jitter numbers for (oif) cei are co mpliant to the oif-ce i-02.0 specification. (12) the hd-sdi and 3g-sdi jitter numbers are compli ant to the smpte292m and smpte424m specifications. (13) the fibre channel transmitter jitter generation numbers are co mpliant to the specification at ? t interoperability point. (14) the fibre channel receiver ji tter tolerance numbers are compliant to the specification at ? r interoperability point. (15) you must use the atx pll adjacent to the transceiver channels to meet the transmitter jitter generation compliance in pcie gen2 8 modes. (16) stratix iv pcie receivers are compli ant to this specificat ion provided the v tx-cm-dc-activeidle-delta of the upstream transmitter is less than 50mv. (17) the jitter numbers fo r serial attached scsi (sas) are co mpliant to the sas -2.1 specification. (18) the jitter numbers for cpri are comp liant to the cpri specification v3.0. (19) the jitter numbers for obsai are compliant to th e obsai rp3 specification v4.1. table 1?30. transceiver block jitter specifications for stratix iv gx devices (1) , (2) (part 9 of 9) symbol/ description conditions ?2 commercial speed grade ?3 commercial/ industrial and ?2 commercial speed grade ?3 military (3) and ?4 commercial/ industrial speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?45 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum table 1?31 lists the transceiver jitter specifications for protocols supported by stratix iv gt devices. table 1?31. transceiver jitter specifications for protocols by stratix iv gt devices (part 1 of 2) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max xlaui/caui transmit jitter generation (1) , (3) total jitter pattern = prbs-31 v od = 800 mv refclk = 644.53 mhz 4 (xlaui)/ 10 (caui) channels in basic 1 mode ? ? 0.30 ? ? 0.30 ? ? 0.30 ui deterministic jitter ? ? 0.17 ? ? 0.17 ? ? 0.17 ui xlaui/caui receiver jitter tolerance (1) total jitter tolerance pattern = prbs-31 > 0.62 > 0.62 ? ui sinusoidal jitter tolerance jitter frequency = 40 khz pattern = prbs-31 equalization = disabled ber = 1e-12 > 5 > 5 ? ui jitter frequency ? 4mhz pattern = prbs-31 equalization = disabled ber = 1e-12 > 0.05 > 0.05 ? ui xfi transmitter jitter generation (2) , (3) total jitter at 10.3125 gbps pattern = prbs-31 vod = 800 mv refclk = 644.53 mhz 10 channels in basic 1 mode ? ? 0.3 ? ? 0.3 ? ? ? ui otl 4.10 (1) , (3) total jitter at 11.18 gbps pattern = prbs-31 v od = 800 mv refclk = 698.75 mhz ? ? 0.30 ? ? 0.30 ? ? 0.30 ui deterministic jitter ? ? 0.17 ? ? 0.17 ? ? 0.17 ui 1?46 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum table 1?32 lists the sfi-s transmitter jitter specifications for stratix iv gt devices. sinusoidal jitter tolerance jitter frequency = 40 khz pattern = prbs-31 equalization = disabled ber = 1e-12 > 5 > 5 ? ui jitter frequency ? 4mhz pattern = prbs-31 equalization = disabled ber = 1e-12 > 0.05 > 0.05 ? ui notes to table 1?31 : (1) the jitter numbers for xlaui/caui are comp liant to the ieee p 802.3ba specification. (2) stratix iv gt transceivers are compliant to the xfi datacom transmitter jitter specifications in table 9 of xfp revision 4.1 . (3) contact altera for board and li nk best practices at ber = 1e-15. table 1?31. transceiver jitter specifications for protocols by stratix iv gt devices (part 2 of 2) symbol/ description conditions ?1 industrial speed grade ?2 industrial speed grade ?3 industrial speed grade unit min typ max min typ max min typ max table 1?32. sfi-s transmitter jitter specifications for stratix iv gt devices (1) , (2) symbol/description conditions -1 industrial speed grade -2 industrial speed grade -3 industrial speed grade unit mean mean mean total transmitter jitter at 11.3 gbps (4) pattern = prbs-31 vod = 800 mv refclk = 706.25 mhz 12 channels in basic 1 mode 0.23 ui (3) ??u i notes to table 1?32 : (1) dedicated refclk pins were used to dri ve the input reference clocks. (2) the jitter numbers are valid for stated conditions only. (3) two hundred channels were characterized to derive the mean transmi tter jitter specification of 0.23 ui. the maximum jitter a cross the 200 units characterized was 0.30 ui. (4) contact altera for board and li nk best practices at ber = 1e-15. chapter 1: dc and switching characteristics for stratix iv devices 1?47 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum transceiver datapath pcs latency f for more information about: basic mode pcs latency, refer to figure 1-90 through figure 1-97 in the transceiver architecture in stratix iv devices chapter. pcie mode pcs latency, refe r to figure 1-102 in the transceiver architecture in stratix iv devices chapter. xaui mode pcs latency, refer to figure 1-119 in the transceiver architecture in stratix iv devices chapter. gige mode pcs latency, refer to figure 1-128 in the transceiver architecture in stratix iv devices chapter. sonet/sdh mode pcs latency, re fer to figure 1-136 in the transceiver architecture in stratix iv devices chapter. sdi mode pcs latency, refer to figure 1-141 in the transceiver architect ure in stratix iv devices chapter. (oif) cei phy mode pcs latency, refer to figure 1-143 in the transceiver architecture in stratix iv devices chapter. core performance specifications this section describes the clock tree, phase-locked loop (pll), digital signal processing (dsp), trimatrix, configuration, jtag, and chip-wide reset ( dev_clrn ) specifications. for the stratix iv gt ?1 and ?2 speed grade specifications, refer to the ?2/?2 speed grade column. for the stratix iv gt ?3 speed grade specification, refer to the ?3 speed grade column, unless otherwise specified. clock tree specifications table 1?33 lists the clock tree specifications for stratix iv devices. table 1?33. clock tree performance for stratix iv devices performance unit symbol ?2/?2 speed grade ?3 speed grade ?4 speed grade global clock and regional clock 800 700 500 mhz periphery clock 550 500 500 mhz 1?48 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum pll specifications table 1?34 lists the stratix iv pll specifications when operating in the commercial (0 to 85c), industrial (?40 to 100c), and military (?55c to 125c) junction temperature ranges. table 1?34. pll specifications for stratix iv devices (part 1 of 2) symbol parameter min typ max unit f in input clock frequency (?2/?2x speed grade) 5 ? 800 (1) mhz input clock frequency (?3 speed grade) 5 ? 717 (1) mhz input clock frequency (?4 speed grade) 5 ? 717 (1) mhz f inpfd input frequency to the pfd 5 ? 325 mhz f vco (2) pll vco operating range (?2 speed grade) 600 ? 1600 mhz pll vco operating range (?3 speed grade) 600 ? 1300 mhz pll vco operating range (?4 speed grade) 600 ? 1300 mhz t einduty input clock or external feedback clock input duty cycle 40 ? 60 % f out output frequency for internal global or regional clock (?2/?2x speed grade) ? ? 800 (3) mhz output frequency for internal global or regional clock (?3 speed grade) ? ? 717 (3) mhz output frequency for internal global or regional clock (?4 speed grade) ? ? 717 (3) mhz f out_ext output frequency for external clock output (?2 speed grade) ? ? 800 (3) mhz output frequency for external clock output (?3 speed grade) ? ? 717 (3) mhz output frequency for external clock output (?4 speed grade) ? ? 717 (3) mhz t outduty duty cycle for external clock output (when set to 50%) 45 50 55 % t fcomp external feedback clock compensation time ? ? 10 ns t configpll time required to reconfigure scan chain ? 3.5 ? scanclk cycles t configphase time required to reconfigure phase shift ? 1 ? scanclk cycles f scanclk scanclk frequency ? ? 100 mhz t lock time required to lock from end-of-device configuration or de-assertion of areset ?? 1 ms t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) ?? 1 ms f clbw pll closed-loop low bandwidth ? 0.3 ? mhz pll closed-loop medium bandwidth ? 1.5 ? mhz pll closed-loop high bandwidth (8) ?4 ? mhz t pll_pserr accuracy of pll phase shift ? ? 50 ps t areset minimum pulse width on the areset signal 10 ? ? ns t inccj (4) , (5) input clock cycle to cycle jitter (f ref 100 mhz) ? ? 0.15 ui (p-p) input clock cycle to cycle jitter (f ref < 100 mhz) ? ? 750 ps (p-p) t outpj_dc (6) period jitter for dedicated clock output (f out 100 mhz) ? ? 175 ps (p-p) period jitter for dedicated clock output (f out < 100 mhz) ? ? 17.5 mui (p-p) chapter 1: dc and switching characteristics for stratix iv devices 1?49 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum t outccj_dc (6) cycle to cycle jitter for dedicated clock output (f out 100 mhz) ? ? 175 ps (p-p) cycle to cycle jitter for dedicated clock output (f out < 100 mhz) ? ? 17.5 mui (p-p) t outpj_io (6) , (9) period jitter for clock output on regular i/o (f out 100 mhz) ? ? 600 ps (p-p) period jitter for clock output on regular i/o (f out < 100 mhz) ? ? 60 mui (p-p) t outccj_io (6) , (9) cycle to cycle jitter for clock output on regular i/o (f out 100 mhz) ? ? 600 ps (p-p) cycle to cycle jitter for clock output on regular i/o (f out < 100 mhz) ? ? 60 mui (p-p) t casc_outpj_dc (6) , (7) period jitter for dedicated clock output in cascaded plls (f out 100mhz) ? ? 250 ps (p-p) period jitter for dedicated clock output in cascaded plls (f out < 100mhz) ? ? 25 mui (p-p) f drift frequency drift after pfdena is disabled for duration of 100 us ? ? 10 % notes to table 1?34 : (1) this specification is limited in the qu artus ii software by the i/o m aximum frequency. the maximu m i/o frequency is differen t for each i/o standard. (2) the vco frequency reported by the quar tus ii software in the pll summary section of the compilation report takes into consideration the vco post-scale counter k value. therefore, if the counter k has a va lue of 2, the frequency report ed can be lower than the f vco specification. (3) this specification is limited by the lower of the two: i/o f max or f out of the pll. (4) a high input jitter directly affects th e pll output jitter. to have low pll output clock jitter, you must provide a clean cl ock source that is less than 120 ps. (5) f ref is fin/n when n = 1. (6) peak-to-peak jitter with a probability level of 10 ?12 (14 sigma, 99.99999999974404% confidence level). the output jitter specification applies to the intrinsic jitter of the pl l, when an input jitter of 30 ps is applied. the external memory interface clock output jitter specifications use a different measurement method and are available in table 1?51 on page 1?62 . (7) the cascaded pll specification is only applicable with the following condition: a. upstream pll: 0.59mhz d upstream pll bw < 1 mhz b. downstream pll: downstream pll bw > 2 mhz (8) high bandwidth pll settings are not supported in external feedback mode. (9) external memory interface clock output jitter specifications use a different m easurement method, which is available in table 1?49 on page 1?61 . table 1?34. pll specifications for stratix iv devices (part 2 of 2) symbol parameter min typ max unit 1?50 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum dsp block specifications table 1?35 lists the stratix iv dsp block performance specifications. table 1?35. block performance specifications for stratix iv dsp devices (1) mode resources used performance unit number of multipliers ?1 industrial and?2/?2 commercial/ industrial speed grade ?3 commercial speed grade ?3 industrial speed grade ?4 commercial speed grade ?4 industrial speed grade 99-bit multiplier (a, c, e, g) (2) 1 520 460 460 400 400 mhz 99-bit multiplier (b, d, f, h) (2) 1 520 460 460 400 400 mhz 1212-bit multiplier (a, e) (3) 1 540 500 500 440 440 mhz 1212-bit multiplier (b, d, f, h) (3) 1 540 500 500 440 430 mhz 1818-bit multiplier 1 600 550 550 480 480 mhz 3636-bit multiplier 1 480 440 440 380 380 mhz 1818-bit multiply accumulator 4 490 440 440 380 380 mhz 1818-bit multiply adder 4 510 470 470 410 400 mhz 1818-bit multiply adder-signed full precision 2 490 450 440 390 390 mhz 1818-bit multiply adder with loopback (4) 2 390 350 350 310 300 mhz 36-bit shift (32-bit data) 1 490 440 440 380 380 mhz double mode 1 480 440 440 380 370 mhz notes to table 1?35 : (1) maximum is for fully pipelined block with round and saturation disabled. (2) the dsp block implements eight independent 9b9b multiplies usin g a, b, c, d for the top dsp half block and e, f, g, h for t he bottom dsp half block multipliers. (3) the dsp block implements six independent 12b12b multiplies using a, b, d for the top dsp half block and e, f, h for the bot tom dsp half block multipliers. (4) maximum for loopback in put registers disabled, round and saturation disabled, and pipeline and output registers enabled. chapter 1: dc and switching characteristics for stratix iv devices 1?51 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum trimatrix memory block specifications table 1?36 lists the stratix iv trimatrix memory block specifications. table 1?36. trimatrix memory block performance specifications for stratix iv devices (1) (part 1 of 2) memory mode resources used performance aluts trimatrix memory ?1 industrial and ?2 /?2 commercial/ industrial speed grade ?3 commercial/ industrial/ military speed grade ?4 commercial/ industrial speed grade ?3 industrial/ military speed grade (2) ?4 industrial speed grade (2) unit mlab (3) single port 6410 0 1 600 500 450 500 450 mhz simple dual-port 3220 0 1 600 500 450 500 450 mhz simple dual-port 6410 0 1 600 500 450 500 450 mhz rom 6410 0 1 600 500 450 500 450 mhz rom 3220 0 1 600 500 450 500 450 mhz m9k block (3) single-port 25636 0 1 600 540 475 540 475 mhz simple dual-port 25636 0 1 550 490 420 490 420 mhz simple dual-port 25636, with the read-during-write option set to old data 0 1 375 340 300 340 300 mhz true dual port 51218 0 1 490 430 370 430 370 mhz true dual-port 51218, with the read-during-write option set to old data 0 1 375 335 290 335 290 mhz rom 1 port 0 1 600 540 475 540 475 mhz rom 2 port 0 1 600 540 475 540 475 mhz min pulse width (clock high time) ? ? 750 800 850 800 850 ps min pulse width (clock low time) ? ? 500 625 690 625 690 ps 1?52 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum configuration and jtag specifications table 1?37 lists the stratix iv configuration mode specifications. m144k block (3) single-port 4k36 0 1 475 440 380 400 350 mhz simple dual-port 2k72 0 1 465 435 385 375 325 mhz simple dual-port 2k72, with the read-during-write option set to old data 0 1 260 240 205 225 200 mhz simple dual-port 2k64 (with ecc) 0 1 335 300 255 295 250 mhz true dual-port 4k36 0 1 400 375 330 350 310 mhz true dual-port 4k36, with the read-during-write option set to old data 0 1 245 230 205 225 200 mhz rom 1 port 0 1 540 500 435 450 420 mhz rom 2 port 0 1 500 465 400 425 400 mhz min pulse width (clock high time) ? ? 700 755 860 860 950 ps min pulse width (clock low time) ? ? 500 625 690 690 690 ps notes to table 1?36 : (1) to achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on -chip pll set to 50% output duty cycle. u se the quartus ii software to repo rt timing for this and other memory block clocking schemes. (2) this is only applicable to the stratix iv e and gx devices. (3) when you use the error detection crc f eature, there is no degradation in f max . table 1?36. trimatrix memory block performance specifications for stratix iv devices (1) (part 2 of 2) memory mode resources used performance aluts trimatrix memory ?1 industrial and ?2 /?2 commercial/ industrial speed grade ?3 commercial/ industrial/ military speed grade ?4 commercial/ industrial speed grade ?3 industrial/ military speed grade (2) ?4 industrial speed grade (2) unit table 1?37. configuration mode specifications for stratix iv devices programming mode dclk f max unit min typ max passive serial ? ? 125 mhz fast passive parallel (1) ??125mhz fast active serial 17 26 40 mhz chapter 1: dc and switching characteristics for stratix iv devices 1?53 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum table 1?38 lists the jtag timing parameters and values for stratix iv devices. temperature sensing diode specifications table 1?39 lists the specifications for the stratix iv temperature sensing diode. table 1?40 lists the specifications for the strati x iv internal temperature sensing diode. remote update only in fast as mode 4.3 5.3 10 mhz note to table 1?37 : (1) this denotes the m aximum frequency supported in the fpp confi guration scheme. the fr equency supported for each device may vary depending on device dens ity. for more information, refer to the configuration, design security, and remote system upgrades in stratix iv devices chapter. table 1?38. jtag timing parameters and values for stratix iv devices symbol description min max unit t jcp tck clock period 30 ? ns t jch tck clock high time 14 ? ns t jcl tck clock low time 14 ? ns t jpsu (tdi) tdi jtag port setup time 1 ? ns t jpsu (tms) tms jtag port setup time 3 ? ns t jph jtag port hold time 5 ? ns t jpco jtag port clock to output ? 11 (1) ns t jpzx jtag port high impedance to valid output ? 14 (1) ns t jpxz jtag port valid output to high impedance ? 14 (1) ns note to table 1?38 : (1) a 1 ns adder is required for each v ccio voltage step down from 3.0 v. for example, t jpco = 12 ns if v ccio of the tdo i/o bank = 2.5 v, or 13 ns if it equals 1.8 v. table 1?39. external temperature sensing diode specifications for stratix iv devices description min typ max unit i bias , diode source current 8 ? 500 ?a v bias, voltage across diode 0.3 ? 0.9 v series resistance ? ? < 5 ? diode ideality factor 1.026 1.028 1.030 ? table 1?37. configuration mode specifications for stratix iv devices programming mode dclk f max unit min typ max table 1?40. internal temperature sensing diode specifications for stratix iv devices temperature range accuracy offset calibrated option sampling rate conversion time resolution minimum resolution with no missing codes ?40 to 100 c 8 c no frequency: 500 khz, 1 mhz < 100 ms 8 bits 8 bits 1?54 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum chip-wide reset (dev_clrn) specifications table 1?41 lists the specifications for the stratix iv chip-wide reset ( dev_clrn ). this specifications denote the minimum pulse width of the dev_clrn signal required to clear all the device registers. periphery performance this section describes periphery performanc e, including high-speed i/o and external memory interface. i/o performance supports several system interfaces, such as the lvds high-speed i/o interface, external memory interface, and the pci/pci-x bus interface. general-purpose i/o standards such as 3. 3-, 2.5-, 1.8-, and 1.5-lvttl/lvcmos are capable of typical 167 mhz and 1.2 lvcmos at 100 mhz interfacing frequency with 10 pf load. for the stratix iv gt ?1 and ?2 speed grade specifications, refer to the ?2/?2 speed grade column. for the stratix iv gt ?3 speed grade specification, refer to the ?3 speed grade column, unless otherwise specified. 1 actual achievable frequency depends on design- and system-specific factors. you must perform hspice/ibis simulations base d on your specific design and system setup to determine the maximum achievable frequency in your system. high-speed i/o specification table 1?42 lists the high-speed i/o ti ming for stratix iv devices. table 1?41. chip-wide reset (dev_clrn) specifications description min typ max unit dev_clrn 500 ? ? ?s table 1?42. high-speed i/o specifications (1), (2) (part 1 of 3) symbol conditions ?2/?2 speed grade ?3 speed grade ?4 speed grade unit min typ max min typ max min typ max f hsclk_in (input clock frequency) true differential i/o standards clock boost factor w = 1 to 40 (3) 5? 800 (4) 5 ? 717 5 ? 717 mhz f hsclk_in (input clock frequency) single ended i/o standards (12) clock boost factor w = 1 to 40 (3) 5 ? 800 5 ? 717 5 ? 717 mhz f hsclk_in (input clock frequency) single ended i/o standards (13) clock boost factor w = 1 to 40 (3) 5 ? 520 5 ? 420 5 ? 420 mhz f hsclk_out (output clock frequency) ?5? 800 (9) 5? 717 (9) 5? 717 (9) mhz chapter 1: dc and switching characteristics for stratix iv devices 1?55 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum transmitter true differential i/o standards - f hsdr (data rate) serdes factor j = 3 to 10 (10) , (11) (5) ? 1600 (5) ?1250 (5) ? 1250 mbps serdes factor j = 2, uses ddr registers (5) ? (6) (5) ? (6) (5) ? (6) mbps serdes factor j = 1, uses an sdr register (5) ? (6) (5) ? (6) (5) ? (6) mbps emulated differential i/o standards with three external output resistor networks - f hsdr (data rate) (7) serdes factor j = 4 to 10 (5) ? 1250 (5) ?1152 (5) ? 800 mbps emulated differential i/o standards with one external output resistor - f hsdr (data rate) (5) ?311 (5) ? 200 (5) ? 200 mbps t x jitter - true differential i/o standards total jitter for data rate, 600 mbps to 1.6 gbps ? ? 160 ? ? 160 ? ? 160 ps total jitter for data rate, < 600 mbps ? ? 0.1 ? ? 0.1 ? ? 0.1 ui t x jitter - emulated differential i/o standards with three external output resistor network total jitter for data rate, 600 mbps to 1.25 gbps ? ? 300 ? ? 300 ? ? 325 ps total jitter for data rate < 600 mbps ?? 0.2 ?? 0.2 ??0.25 ui t x jitter - emulated differential i/o standards with one external output resistor network ? ? ? 0.125 ? ? 0.15 ? ? 0.15 ui t duty tx output clock duty cycle for both true and emulated differential i/o standards 45 50 55 45 50 55 45 50 55 % t rise & t fall true differential i/o standards ? ? 160 ? ? 200 ? ? 200 ps emulated differential i/o standards with three external output resistor networks ? ? 250 ? ? 250 ? ? 300 ps emulated differential i/o standards with one external output resistor ? ? 460 ? ? 500 ? ? 500 ps table 1?42. high-speed i/o specifications (1), (2) (part 2 of 3) symbol conditions ?2/?2 speed grade ?3 speed grade ?4 speed grade unit min typ max min typ max min typ max 1?56 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum tccs true differential i/o standards ? ? 100 ? ? 100 ? ? 100 ps emulated differential i/o standards ? ? 250 ? ? 250 ? ? 250 ps receiver true differential i/o standards - f hsdrdpa (data rate) serdes factor j = 3 to 10 (11) 150 ? 1600 150 ? 1250 150 ? 1250 mbps f hsdr (data rate) serdes factor j = 3 to 10 (5) ? (8) (5) ? (8) (5) ? (8) mbps serdes factor j = 2, uses ddr registers (5) ? (6) (5) ? (6) (5) ? (6) mbps serdes factor j = 1, uses an sdr register (5) ? (6) (5) ? (6) (5) ? (6) mbps dpa mode dpa run length ? ? ? 10000 ? ? 10000 ? ? 10000 ui soft cdr mode soft-cdr ppm tolerance ? ? ? 300 ? ? 300 ? ? 300 ppm non dpa mode sampling window ? ? ? 300 ? ? 300 ? ? 300 ps notes to table 1?42 : (1) when j = 3 to 10, use the serializer/deserializer (serdes) block. (2) when j = 1 or 2, bypass the serdes block. (3) clock boost factor (w) is the ratio between input data rate to the input clock rate. (4) for 820, 530, 360, and 290 density devices, the frequency is 762 mhz. (5) the minimum specification depe nds on the clock source (for example, the pll an d clock pin) and the clock routing resource (g lobal, regional, or local) that you use. the i/o differential buffer and inpu t register do not have a minimum toggle rate. (6) the maximum ideal frequency is the serdes factor (j) x the pll maximum output frequency (f out ) provided you can close th e design timi ng and the signal integrity si mulation is clean. (7) you must calculate the leftover timing margin in the receiver by performing li nk timing closure analys is. you must consider the board skew margin, transmitter channel-to-channel skew , and receiver sampling ma rgin to determine le ftover timing margin. (8) you can estimate the achievable maximum data rate for non-dpa mode by perfor ming link timing closure analysis. you must cons ider the board skew margin, transmitter delay margin, and the receiver sampling margin to determ ine the maximum data rate supported. (9) this is achieved by using th e lvds and dpa clock network. (10) if the receiver with dpa enabled and transmitter are using shared plls, the minimu m data rate is 150 mbps. (11) the f max specification is based on the fast clock used for serial data. the interface f max also depends on the parallel clock domain, which is design dependent and requires timing analysis. (12) this only applies to dpa and soft-cdr modes. (13) this only applies to lv ds source synchronous mode. table 1?42. high-speed i/o specifications (1), (2) (part 3 of 3) symbol conditions ?2/?2 speed grade ?3 speed grade ?4 speed grade unit min typ max min typ max min typ max chapter 1: dc and switching characteristics for stratix iv devices 1?57 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum table 1?43 lists the dpa lock time specifications for stratix iv es devices. figure 1?4 shows the dpa lock time specifications with dpa pll calibration enabled. table 1?43. dpa lock time specifications?stratix iv es devices only (1) , (2) , (3) standard training pattern number of data transitions in one repetition of training pattern number of repetitions per 256 data transitions (4) condition maximum spi-4 00000000001111111111 2 128 without dpa pll calibration 256 data transitions with dpa pll calibration 3x256 data transitions + 2x96 slow clock cycles (5) parallel rapid i/o 00001111 2 128 without dpa pll calibration 256 data transitions with dpa pll calibration 3x256 data transitions + 2x96 slow clock cycles (5) 10010000 4 64 without dpa pll calibration 256 data transitions with dpa pll calibration 3x256 data transitions + 2x96 slow clock cycles (5) miscellaneous 10101010 8 32 without dpa pll calibration 256 data transitions with dpa pll calibration 3x256 data transitions + 2x96 slow clock cycles (5) 01010101 8 32 without dpa pll calibration 256 data transitions with dpa pll calibration 3x256 data transitions + 2x96 slow clock cycles (5) notes to table 1?43 : (1) the dpa lock time is for one channel. (2) one data transition is defined as a 0-to-1 or 1-to-0 transition. (3) the dpa lock time applie s to commercial, industrial, and military speed grades. (4) this is the number of repetiti on for the stated trai ning pattern to achieve 256 data transitions. (5) slow clock = data rate (m bps)/deserialization factor. figure 1?4. dpa lock time specification with dpa pll calibration enabled rx_dpa_locked rx_reset dpa lock time 256 data transitions 96 slow clock cycles 256 data transitions 256 data transitions 96 slow clock cycles 1?58 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum table 1?44 lists the dpa lock time specifications for stratix iv gx and gt devices. figure 1?5 shows the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate equal to or higher than 1.25 gbps. table 1?45 lists this information in table form. table 1?44. dpa lock time specifications?stratix iv gx and gt devices only (1) , (2) , (3) standard training pattern number of data transitions in one repetition of the training pattern number of repetitions per 256 data transitions (4) maximum spi-4 00000000001111111111 2 128 640 data transitions parallel rapid i/o 00001111 2 128 640 data transitions 10010000 4 64 640 data transitions miscellaneous 10101010 8 32 640 data transitions 01010101 8 32 640 data transitions notes to table 1?44 : (1) the dpa lock time is for one channel. (2) one data transition is defined as a 0-to-1 or 1-to-0 transition. (3) the dpa lock time stated in the table applies to commercial, industrial, and military speed grades. (4) this is the number of repetition s for the stated training pattern to achieve the 256 data transitions. figure 1?5. lvds soft-cdr/dpa sinusoidal jitter tolerance s pecification for a data rate equal to or higher than 1.25 gbps l v ds soft-cdr/dpa sin u soidal jitter tolerance specification f1 f2 f3 f4 jitter fre quency (hz) jitter amphlitude (ui) 0.1 0.35 8.5 25 chapter 1: dc and switching characteristics for stratix iv devices 1?59 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum table 1?45 lists the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate equal to or higher than 1.25 gbps. figure 1?6 shows the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate less than 1.25 gbps. when the data rate is equals to 800 mbps, the lvds soft-cdr/dpa sinusoidal jitter tolerance allows up to 0.1 ui (125 ps) fo r jitter frequencies between 479.9 khz and 20 mhz. dll and dqs logic block specifications table 1?46 lists the dll frequency range specifications for stratix iv devices. table 1?45. lvds soft-cdr/dpa sinusoidal jitter mask values for a data rate equal to or higher than 1.25 gbps jitter frequency (hz) sinusoidal jitter (ui) f1 10,000 25.000 f2 17,565 25.000 f3 1,493,000 0.350 f4 50,000,000 0.350 figure 1?6. lvds soft-cdr/dpa sinusoidal jitter toler ance specification for a data rate less than 1.25 gbps 0.1 ui p-p baud/1667 20 mhz fre quency sin usoidal jitter amplitude 20db/dec table 1?46. dll frequency range specifications for stratix iv devices (part 1 of 2) frequency mode frequency range (mhz) available phase shift dqs delay buffer mode (1) number of delay chains ?2/?2 speed grade ?3 speed grade ?4 speed grade 0 90-140 90-130 90-120 22.5, 45, 67.5, 90 low 16 1 120-180 120-170 120-160 30, 60, 90, 120 low 12 2 150-220 150-210 150-200 36, 72, 108, 144 low 10 3 180-280 180-260 180-240 45, 90,135, 180 low 8 1?60 chapter 1: dc and switching characteristics for stratix iv devices switching characteristics stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum table 1?47 lists the dqs phase offset delay per stage for stratix iv devices. table 1?48 lists the dqs phase shift error for stratix iv devices. 4 240-350 240-320 240-290 30, 60, 90, 120 high 12 5 290-430 290-380 290-360 36, 72, 108, 144 high 10 6 360-540 360-450 360-450 45, 90, 135, 180 high 8 7 470-700 470-630 470-590 60, 120, 180, 240 high 6 note to table 1?46 : (1) low indicates a 6-bit dqs delay setting; high indicates a 5-bit dqs delay setting. table 1?46. dll frequency range specifications for stratix iv devices (part 2 of 2) frequency mode frequency range (mhz) available phase shift dqs delay buffer mode (1) number of delay chains ?2/?2 speed grade ?3 speed grade ?4 speed grade table 1?47. dqs phase offset delay per setting for stratix iv devices (1) , (2) , (3) speed grade min max unit ?2/?2 7 13 ps ?3 7 15 ps ?4 7 16 ps notes to table 1?47 : (1) the valid settings for phase offset ar e -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes 4 to 6. (2) the typical value equals the averag e of the minimum and maximum values. (3) the delay settings are linear, with a cumulative delay variation of 40 ps for all speed grades. for example, when using a ?2 speed grade and applying a 10 phase offset settings to a 90 phase shift at 400 mhz, the expected average cumulative delay is [625 ps + (10 10.5 ps) 20 ps] = 730 ps 20 ps. table 1?48. dqs phase shift error specification for dll-delayed clock (t dqs_pserr ) for stratix iv devices (1) number of dqs delay buffer ?2/?2x speed grade ?3 speed grade ?4 speed grade unit 1262830ps 2525660ps 3788490ps 4 104 112 120 ps note to table 1?48 : (1) this error specificat ion is the absolute maximum and minimum error. for exam ple, skew on three dqs delay buffers in a ?2/?2x speed grade is 78 ps or 39 ps. chapter 1: dc and switching characteristics for stratix iv devices 1?61 switching characteristics march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum table 1?49 lists the memory output clock jitter specifications for stratix iv devices. oct calibration block specifications table 1?50 lists the oct calibration block specifications for stratix iv devices. table 1?49. memory output clock jitter specification for stratix iv devices (1) , (2) , (3) , (4) parameter clock network symbol ?2/?2x speed grade ?3 speed grade ?4 speed grade unit min max min max min max clock period jitter regional t jit(per) -5050-5555-5555ps cycle-to-cycle period jitter regional t jit(cc) -100 100 -110 110 -110 110 ps duty cycle jitter regional t jit(duty) -50 50 -82.5 82.5 -82.5 82.5 ps clock period jitter global t jit(per) -75 75 -82.5 82.5 -82.5 82.5 ps cycle-to-cycle period jitter global t jit(cc) -150 150 -165 165 -165 165 ps duty cycle jitter global t jit(duty) -7575-9090-9090ps notes to table 1?49 : (1) the memory output clock jitter measurements are for 200 con secutive clock cycles, as specified in the je dec ddr2/ddr3 sdram standard. (2) the clock jitter specificati on applies to memory output clock pins generate d using differential signal-splitter and ddio cir cuits clocked by a pll output routed on a regional or global clock network as specified. altera recommends using regional clock ne tworks whenever poss ible. (3) the memory output clock jitter stated in table 1?49 is applicable when an inpu t jitter of 30 ps is applied. (4) the clock jitter specification is characterized with 70% util ization, 266 mhz core clock frequency, and 12.5% design toggle rate. if your design exceeds any of these conditio ns, the jitter specification of the design may not meet the above specification. table 1?50. oct calibration block specifications for stratix iv devices symbol description min typ max unit octusrclk clock required by oct calibration blocks ? ? 20 mhz t octcal number of octusrclk clock cycles required for oct r s /r t calibration ? 1000 ? cycles t octshift number of octusrclk clock cycles required for oct code to shift out ? 28 ? cycles t rs_rt time required between the dyn_term_ctrl and oe signal transitions in a bidirectional i/o buffer to dynamically switch between oct r s and r t ?2.5? ns 1?62 chapter 1: dc and switching characteristics for stratix iv devices i/o timing stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum figure 1?7 shows the timing diagram for the oe and dyn_term_ctrl signals. duty cycle distorti on (dcd) specifications table 1?51 lists the worst-case dcd for stratix iv devices. i/o timing altera offers two ways to determine i/o timing?the excel-based i/o timing and the quartus ii timing analyzer. excel-based i/o timing provides pin timing performance for each device density and speed grade. the data is typically used prior to designing the fpga to get an estimate of the timing budget as part of the li nk timing analysis. the quartus ii timing analyzer provides a more accurate and precise i/o timing data based on the specifics of the design after you complete place-and-route. f the excel-based i/o timing spreadsheet is downloadable from the literature: stratix iv devices webpage. figure 1?7. timing diagram for the oe and dyn_term_ctrl signals table 1?51. worst-case dcd on stratix iv i/o pins (1) symbol ?2/?2 speed grade ?3 speed grade ?4 speed grade unit min max min max min max output duty cycle 45 55 45 55 45 55 % note to table 1?51 : (1) the listed specification is only applicable to the output buffer across different i/o standards. dyn_term_ctrl oe r x r x tristate tristate t x t rs_rt t rs_rt chapter 1: dc and switching characteristics for stratix iv devices 1?63 i/o timing march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum programmable ioe delay table 1?52 lists the stratix iv ioe programmable delay settings. programmable output buffer delay table 1?53 lists the delay chain settings that control the rising and falling edge delays of the output buffer. the default delay is 0 ps. table 1?52. ioe programmable delay for stratix iv devices parameter (1) available settings min offset (2) fast model slow model industrial/ military commercial (3) c2 (3) c3 c4 i3/m3 i4 unit d1 16 0 0.462 0.505 0.732 0.795 0.857 0.801 0.864 ns d2 8 0 0.234 0.232 0.337 0.372 0.407 0.371 0.405 ns d3 8 0 1.700 1.769 2.695 2.927 3.157 2.948 3.178 ns d4 16 0 0.508 0.554 0.813 0.882 0.952 0.889 0.959 ns d5 16 0 0.472 0.500 0.747 0.799 0.875 0.817 0.882 ns d6 7 0 0.186 0.195 0.294 0.319 0.345 0.321 0.347 ns notes to table 1?52 : (1) you can set this value in th e quartus ii software by selecting d1 , d2 , d3 , d4 , d5 , and d6 in the assignment name column. (2) minimum offset does not include the intrinsic delay. (3) for the ep4sgx530 device density, the ioe progra mmable delays have an additi onal 5% maximum offset. table 1?53. programmable output buffer delay (1) symbol parameter typical unit d outbuf rising and/or falling edge delay 0 (default) ps 50 ps 100 ps 150 ps note to table 1?53 : (1) you can set the progra mmable output buffer de lay in the quartus ii software by setting the output buffer delay control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the output buffer delay assignment. 1?64 chapter 1: dc and switching characteristics for stratix iv devices glossary stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum glossary table 1?54 lists the glossary for this chapter. table 1?54. glossary table (part 1 of 4) letter subject definitions a, b, c ?? d differential i/o standards receiver input waveforms transmitter output waveforms e ?? f f hsclk left/right pll input clock frequency. f hsdr high-speed i/o block: maximum/minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa high-speed i/o block: maximum/minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. g, h, i ?? single-ended waveform differential waveform positive channel (p) = v ih negative channel (n) = v il ground v id v id v id p ? n = 0 v v cm single-ended waveform differential waveform positive channel (p) = v oh negative channel (n) = v ol ground v od v od v od p ? n = 0 v v cm chapter 1: dc and switching characteristics for stratix iv devices 1?65 glossary march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum j j high-speed i/o block: deserialization factor (width of parallel data bus). jtag timing specifications jtag timing specifications: k, l, m, n, o ?? p pll specifications diagram of pll specifications (1) note: (1) core clock can only be fed by dedicated clock input pins or pll outputs. q ?? rr l receiver differential input discrete resistor (external to stratix iv device). table 1?54. glossary table (part 2 of 4) letter subject definitions tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms core clock external feedback reconfigurable in user mode key clk n m pfd switchover vco cp lf clkout pins gclk rclk f inpfd f in f vco f out f out_ext counters c0..c9 1?66 chapter 1: dc and switching characteristics for stratix iv devices glossary stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum s sw (sampling window) timing diagram?the period of time during which the data must be valid in order to capture it correctly. the setup and hold times determine the ideal strobe position within the sampling window, as shown: single-ended voltage referenced i/o standard the jedec standard for sstl and hstl i/o defines both the ac and dc input signal values. the ac values indicate the voltage levels at which the receiver must meet its timing specifications. the dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. after the receiver input has crossed the ac value, the receiver changes to the new logic state. the new logic state is then maintained as long as the input stays beyond the ac threshold. this approach is intended to provide predictable receiver timing in the presence of input waveform ringing, as shown: single-ended voltage referenced i/o standard t t c high-speed receiver/transmitter input and output clock period. tccs (channel- to-channel-skew) the timing difference between the fastest and slowest output edges, including t co variation and clock skew, across channels driven by the same pll. the clock is included in the tccs measurement (refer to the timing diagram figure under sw in this table). t duty high-speed i/o block: duty cycle on high-speed transmitter output clock. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c /w ) t fall signal high-to-low transition time (80-20%) t inccj cycle-to-cycle jitter tolerance on the pll clock input t outpj_io period jitter on the general purpose i/o driven by a pll t outpj_dc period jitter on the dedicated clock output driven by a pll t rise signal low-to-high transition time (20-80%) u ?? table 1?54. glossary table (part 3 of 4) letter subject definitions bit time 0.5 x tccs rskm sampling window (sw) rskm 0.5 x tccs v ih ( ac ) v ih(dc) v ref v il(dc) v il(ac ) v oh v ol v ccio v ss chapter 1: dc and switching characteristics for stratix iv devices 1?67 glossary march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum document revision history table 1?55 lists the revision history for this chapter. v v cm(dc) dc common mode input voltage. v icm input common mode voltage?the common mode of the differential signal at the receiver. v id input differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. v dif(ac) ac differential input voltage?minimum ac input differential voltage required for switching. v dif(dc) dc differential input voltage? minimum dc input differential voltage required for switching. v ih voltage input high?the minimum positive voltage applied to the input which is accepted by the device as a logic high. v ih(ac) high-level ac input voltage v ih(dc) high-level dc input voltage v il voltage input low?the maximum positive voltage applied to the input which is accepted by the device as a logic low. v il(ac) low-level ac input voltage v il(dc) low-level dc input voltage v ocm output common mode voltage?the common mode of the differential signal at the transmitter. v od output differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. v swing differential input voltage v x input differential cross point voltage v ox output differential cross point voltage w w high-speed i/o block: clock boost factor x, y, z ?? table 1?54. glossary table (part 4 of 4) letter subject definitions table 1?55. document revision history (part 1 of 3) date version changes march 2014 5.8 added note to table 1?49 . updated d6 row in table 1?52 . january 2014 5.7 updated table 1?42. december 2013 5.6 updated table 1?23 and table 1?24. november 2013 5.5 updated table 1?23 and table 1?24. november 2013 5.4 updated table 1?42, table 1?23, and table 1?24. july 2012 5.3 added table 1?5 and table 1?40. updated table 1?15, table 1?22, table 1?23, table 1?30, table 1?33, table 1?35, table 1?36, table 1?39, table 1?42 and table 1?51. removed ?schmitt trigger input? section. december 2011 5.2 added figure 1?7. updated table 1?22 and table 1?41. 1?68 chapter 1: dc and switching characteristics for stratix iv devices glossary stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum june 2011 5.1 added military speed grade information. updated table 1?1 and table 1?30. updated (note 3) in table 1?42 and (note 3) in table 1?43. added military speed grade to table 1?5, table 1?10, table 1?11, table 1?23, table 1?30, table 1?36, and table 1?51. april 2011 5.0 updated table 1?1, table 1?5, table 1?6, table 1?13, table 1?16, table 1?23, and table 1?24. march 2011 4.9 updated table 1?24. march 2011 4.8 removed (note 17) in table 1-24. february 2011 4.7 added (note 17) to table 1?24. february 2011 4.6 updated table 1?1, table 1?5, table 1?23, table 1?24, table 1?30, table 1?31, table 1?32, table 1?34, table 1?37, table 1?41, and table 1?51. updated the ?recommended operating conditions? section. added the ?schmitt trigger input? section.march minor text edits. november 2010 4.5 updated table 1?29. updated chapter title. minor text edits. september 2010 4.4 applied new template. updated table 1?1 and table 1?5. july 2010 4.3 updated table 1?7, table 1?22, table 1?23, table 1?33, table 1?35, table 1?36, and table 1?40. added table 1?39. changed ?pci express? to ?pcie? throughout. minor text edits march 2010 4.2 updated table 1?22, table 1?23, table 1?30, table 1?46, and table 1?49. added table 1?31. minor text edits. february 2010 4.1 updated table 1?11, table 1?22, table 1?23, table 1?24, table 1?25, table 1?26, table 1?27, table 1?29, table 1?32, table 1?33, table 1?34, table 1?35, table 1?39, table 1?40, table 1?43, table 1?46, and table 1?49. added stratix iv gt speed grade note to table 1?32, table 1?35, table 1?39, table 1?43, table 1?44, table 1?45, and table 1?46. added table 1?28 and table 1?30. minor text edits. table 1?55. document revision history (part 2 of 3) date version changes chapter 1: dc and switching characteristics for stratix iv devices 1?69 glossary march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum november 2009 4.0 added table 1?9, table 1?15, table 1?38, and table 1?39. added figure 1?5 and figure 1?6. added the ?transceiver data path pcs latency? section. updated the ?electrical characteristics?, ?operating conditions?, and ?i/o timing? sections. all tables updated except table 1?16, table 1?24, table 1?25, table 1?26, table 1?27, table 1?33, table 1?34, and table 1?45. updated figure 1?2 and figure 1?3. updated equation 1?1. deleted table 1-28, table 1-29, table 1-30, table 1-42, table 1-43, and table 1-44. minor text edits. june 2009 3.1 added ?preliminary specifications? to the footer of each page. updated table 1?1, table 1?2, table 1?7, table 1?10, table 1?11, table 1?12, table 1?21, table 1?22, table 1?23, table 1?25, table 1?37, table 1?38, table 1?39, table 1?40, and table 1?44. minor text edits. march 2009 3.0 replaced t able 1?31 and table 1?37. updated table 1?1, table 1?2, table 1?5, table 1?19, table 1?41, table 1?44, table 1?45, table 1?49, and table 1?51. added table 1?21, table 1?46, and table 1?47 added figure 1?3. removed ?timing model?, ?preliminary and final timing?, ?i/o timing measurement methodology?, ?i/o default capacitive loading?, and ?referenced documents? sections. december 2008 2.1 minor changes. november 2008 2.0 minor text edits. updated table 1?19, table 1?32, table 1?34 - table 1?39. minor text edits. august 2008 1.1 updated table 1?1, table 1?2, table 1?4, table 1?5, and table 1?26. removed figures from ?transceiver performance specifications? on page 1?10 that are repeated in the glossary. minor text edits and an additional note to table 1?26. may 2008 1.0 initial release. table 1?55. document revision history (part 3 of 3) date version changes 1?70 chapter 1: dc and switching characteristics for stratix iv devices glossary stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum siv54002-1.5 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 4: device datasheet and addendum february 2011 feedback subscribe iso 9001:2008 registered 2. addendum to the stratix iv device handbook this chapter describes changes to the published version of the stratix iv device handbook. all changes from revision 1.4 of this chapter are now incorporated in the main handbook chapters or in an 612: decision feedback equalization in stratix iv devices . adaptive equalization (aeq) f this aeq information is now located in the dynamic reconfiguration in stratix iv devices chapter. decision feedback equalization (dfe) f for more information about the dfe feature, refer to an 612: decision feedback equalization in stratix iv devices . power-on reset circuitry the power-on reset circuitry information is now located in the hot socketing and power-on reset in stratix iv devices chapter. power-on reset specifications f the power-on reset specification in formation is now located in the hot socketing and power-on reset in stratix iv devices chapter. february 2011 siv54002-1.5 2?2 chapter 2: addendum to the stratix iv device handbook stratix iv device handbook february 2011 altera corporation volume 4: device datasheet and addendum document revision history table 2?1 lists the revision history for this chapter. table 2?1. document revision history date version changes february 2011 1.5 removed the ?decision feedback equalization (dfe)? section now that an 612: decision feedback equalization in stratix iv devices is published. moved the ?adaptive equalization (aeq)? sections to the dynamic reconfiguration in stratix iv devices chapter. moved the ?power-on reset circuitry? and ?power-on reset specifications? sections to the hot socketing and power-on reset in stratix iv devices chapter. minor text edits. september 2010 1.4 added corrections for the adaptive equalization (aeq) section of the stratix iv dynamic reconfiguration chapter. added new information for the decision feedback equalization (dfe) feature. april 2010 1.3 added corrections for the ?power-on re set circuitry? and ?power-on reset specifications? sections to of the hot socketing and power-on reset in stratix iv devices chapter. march 2010 1.2 moved the ?power-on reset circuitry?, ?p ower-on reset specifications?, ?correct power-up sequence for production devices?, and ?correct power-up sequence for production devices? sections to the hot socketing and power-on reset in stratix iv devices chapter. moved the ?power-on reset circuit? and ?jtag tms and tdi pin pull-up resistor value specification? sections to the configuration, design security, remote system upgrades with stratix iv devices chapter. moved the ?summary of oct assignments? section to the i/o features in stratix iv devices chapter. february 2010 1.1 added the ?power-on reset circuitry?, ?power-on reset specifications?, ?correction to por signal pulse width delay times?, ?correct power-up sequence for production devices?, ?power-on reset circuit?, ?summa ry of oct assignments?, and ?jtag tms and tdi pin pull-up resistor value specification? sections. minor text edits. november 2009 1.0 stratix iv gx enhanced transceiver data rate specifications in ? 4 commercial speed grade. initial release. march 2014 altera corporation stratix iv device handbook volume 4: device datasheet and addendum additional information this chapter provides additional info rmation about the document and altera. about this handbook this handbook provides comprehensive information about the altera ? stratix ? iv family of devices. how to contact altera to locate the most up-to-date informat ion about altera products, refer to the following table. typographic conventions the following table shows the typographic conventions this document uses. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature nontechnical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note to table: (1) you can also contact yo ur local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicate command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, di sk drive names, file names, file name extensions, software utility names, and gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicate document titles. for example, stratix iv design guidelines . italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, 2?2 additional information typographic conventions stratix iv device handbook march 2014 altera corporation volume 4: device datasheet and addendum courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . the suffix n denotes an active-low signal. for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). r an angled arrow instructs you to press the enter key. 1., 2., 3., and a., b., c., and so on numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. h the question mark directs you to a software help system with related information. f the feet direct you to another document or website with related information. m the multimedia icon directs you to a related multimedia presentation. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. the envelope links to the email subscription management center page of the altera website, where you can sign up to receive update notifications for altera documents. visual cue meaning |
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